try to implement comb_mem

2 files changed, 109 insertions, 0 deletions

diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv
new file mode 100644
index 0000000..bbfdcd0
--- /dev/null
+++ b/nandgame/comb_mem.sv
@@ -0,0 +1,56 @@
+`timescale 1us/1us
+
+`include "../my_mem.v"
+
+module comb_mem #(
+  parameter DATA_WIDTH = 16
+) (
+    // store to A register
+    input a_i,
+    // store to D register
+    input d_i,
+    // store to address in memory pointed to by A (currently)
+    input pa_i,
+
+    // value to store
+    input [(DATA_WIDTH-1):0] X,
+    // nandgame updates on falling edge
+    input wire cl,
+
+    output reg [(DATA_WIDTH-1):0] A_o,
+    output reg [(DATA_WIDTH-1):0] D_o,
+    output reg [(DATA_WIDTH-1):0] pA_o
+);
+
+wire inv_clk;
+// my hw uses posedge, nandgame uses negedge.
+assign inv_clk = ~cl;
+
+my_mem #(
+    .DATA_WIDTH(DATA_WIDTH),
+    // limit memory
+    .DATA_DEPTH(1024)
+) nand_memory (
+    .clk_i(inv_clk),
+    .write_en_i(pa_i),
+    .read_en_i(1'b1),
+    .r_read_addr(A_o),
+    .r_write_addr(A_o),
+    .data_o(pA_o),
+    .data_i(X)
+);
+
+initial begin
+    A_o = 0;
+    D_o = 0;
+end
+
+always @(negedge cl) begin
+    if (a_i)
+        A_o <= X;
+
+    if (d_i)
+        D_o <= X;
+end
+
+endmodule
diff --git a/nandgame/comb_mem_tb.sv b/nandgame/comb_mem_tb.sv
new file mode 100644
index 0000000..66a5e64
--- /dev/null
+++ b/nandgame/comb_mem_tb.sv
@@ -0,0 +1,53 @@
+`timescale 1us/1us
+
+module comb_mem_tb;
+
+reg clk_i;
+logic wa, wd, wpa;
+logic [15:0] o_a, o_d, o_pa;
+logic [15:0] X;
+
+comb_mem uut (
+  .cl(clk_i),
+  .a_i(wa),
+  .d_i(wd),
+  .pa_i(wpa),
+  .A_o(o_a),
+  .D_o(o_d),
+  .pA_o(o_pa),
+  .X(X)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+  filename=`DUMP_FILE_NAME;
+`else
+  filename="comb_mem.lxt2";
+`endif
+  $dumpfile(filename);
+  $dumpvars();
+  clk_i = 0;
+  wa = 0; wd = 0; wpa = 0;
+  X = 16'h55;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+
+  repeat(3) @(posedge clk_i);
+  wa = 1;
+  repeat(3) @(posedge clk_i);
+  wa = 0;
+  wd = 1;
+  repeat(3) @(posedge clk_i);
+  wd = 0;
+  wpa = 1;
+  X = 16'haa;
+  repeat(3) @(posedge clk_i);
+
+  $finish();
+end
+
+endmodule