p2s: Fix test bench

use negedge timing

1 files changed, 23 insertions, 25 deletions

diff --git a/par_to_ser.tb.v b/par_to_ser.tb.v
index f6f3d7c..b610884 100644
--- a/par_to_ser.tb.v
+++ b/par_to_ser.tb.v
@@ -3,18 +3,19 @@
 module par_to_ser_tb (
 );
 
-reg clk_i;
-reg rst_i;
-reg data_valid_i;
-reg [7:0] dat_i;
-wire dat_o;
+logic clk_i;
+logic rst_i;
+logic data_valid_i;
+logic [7:0] dat_i;
+logic dat_o;
 
 par_to_ser uut(
   .clk_i(clk_i),
   .rst_i(rst_i),
   .data_valid_i(data_valid_i),
   .dat_i(dat_i),
-  .dat_o(dat_o)
+  .dat_o(dat_o),
+  .dat_valid_o()
 );
 
 string filename;
@@ -25,44 +26,41 @@ initial begin
   filename="par_to_ser.lxt2";
 `endif
   $dumpfile(filename); $dumpvars();
-  clk_i <= 0;
-  rst_i <= 1'b1;
-  data_valid_i <= 1'b0;
+  clk_i = 0;
+  rst_i = 1'b1;
+  data_valid_i = 1'b0;
 
   #1
-  rst_i <= 1'b0;
+  rst_i = 1'b0;
   #1
-  rst_i <= 1'b1;
+  rst_i = 1'b1;
 end
 
 always #10 clk_i = ~clk_i;
 
-integer sollbit = 1'b0;
+bit sollbit = 1'b0;
 
 initial begin
-  #37
+  #13
+  @(negedge clk_i);
 
   for (integer i = 0; i < 255; i++) begin
     // clock data in
-    dat_i <= i;
-    data_valid_i <= 1'b1;
+    dat_i = i;
+    data_valid_i = 1'b1;
 
-    // wait 1 cycle
-    #20
-    data_valid_i <= 1'b0;
+    @(negedge clk_i);
+    data_valid_i = 1'b0;
 
     for (integer j = 0; j < 8; j++) begin
       sollbit = (i >> j) & 1;
-      assert(dat_o == sollbit);
+      assert(dat_o == sollbit)
+      else $error("Expected bit to be %d, but was %d", sollbit, dat_o);
 
-      #20
-      ;
+      @(negedge clk_i);
     end
 
-    // let module do its work
-    #40
-    ;
-
+    repeat(2) @(negedge clk_i);
   end
 
   $finish();