p2s2p: Fix testbench

iverilog syntax error (needs space)
timing
use logic,

1 files changed, 0 insertions, 79 deletions

diff --git a/par_to_ser_to_ser.tb.v b/par_to_ser_to_ser.tb.v
deleted file mode 100644
index 1f30ae2..0000000
--- a/par_to_ser_to_ser.tb.v
+++ /dev/null
@@ -1,79 +0,0 @@
-// converts back and forth
-// parallel > serial > parallel
-
-`timescale 1us/1us
-
-module par_to_ser_tb (
-);
-
-reg clk_i;
-reg rst_i;
-reg data_valid_i;
-reg [7:0] dat_i;
-wire dat_o;
-wire [7:0] dat_o2;
-
-wire send_valid;
-
-par_to_ser uut(
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-  .data_valid_i(data_valid_i),
-  .dat_i(dat_i),
-  .dat_o(dat_o),
-  .dat_valid_o(send_valid)
-);
-
-ser_to_par uut2(
-  .clk_i(clk_i),
-  .rst_i(rst_i),
-
-  .dat_valid_i(send_valid),
-  .dat_i(dat_o),
-
-  .dat_o(dat_o2),
-  .dat_valid_o()
-);
-
-string filename;
-initial begin
-`ifdef DUMP_FILE_NAME
-  filename=`DUMP_FILE_NAME;
-`else
-  filename="par_to_ser.lxt2";
-`endif
-  $dumpfile(filename); $dumpvars();
-  clk_i <= 0;
-  rst_i <= 1'b1;
-  data_valid_i <= 1'b0;
-
-  #1
-  rst_i <= 1'b0;
-  #1
-  rst_i <= 1'b1;
-end
-
-always #10 clk_i = ~clk_i;
-
-initial begin
-  #37
-
-  for (integer i = 0; i < 255; i++) begin
-    // clock data in
-    dat_i <= i;
-    data_valid_i <= 1'b1;
-
-    // wait 1 cycle
-    #20
-    data_valid_i <= 1'b0;
-
-    // let module do its work
-    #200
-    assert(i == dat_o2);
-
-  end
-
-  $finish();
-end
-
-endmodule