diff options
| author | uvok | 2026-01-09 15:18:23 +0100 |
|---|---|---|
| committer | uvok | 2026-01-09 15:18:23 +0100 |
| commit | 6c83fd8730e55de8b1daaac1deb111d3d9bd408e (patch) | |
| tree | 33a3dbc4fd87011b657b193224c3f39c5de6b766 /playground/clkdiv.v | |
| parent | 678cb2d2d752bbac7625ba9b287762b3acabf116 (diff) | |
move stuff around
Diffstat (limited to 'playground/clkdiv.v')
| -rw-r--r-- | playground/clkdiv.v | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/playground/clkdiv.v b/playground/clkdiv.v new file mode 100644 index 0000000..b6f1419 --- /dev/null +++ b/playground/clkdiv.v @@ -0,0 +1,36 @@ +`timescale 1us/1us + +module clkdiv ( + input rst_i, + input clk, // clk input + output reg o_divclk // divided output (must be a reg, b/c it needs to keep state) +); + +reg [23:0] counter; +// CLK is 27 MHz +// we want a 2Hz signal at the output +// and pin needs to *toggle twice* within one period +// 27MHz / 4 = 6750000 +localparam DIVISOR = 24'd6_749_999; + +always @(posedge clk or negedge rst_i) begin + if (!rst_i) + counter <= 24'd0; + else if (counter < DIVISOR) + counter <= counter + 1'b1; + else + counter <= 24'd0; +end + +always @(posedge clk or negedge rst_i) begin + if (!rst_i) + o_divclk <= 1'b0; + else if (counter == DIVISOR) + o_divclk <= ~o_divclk; + else + o_divclk <= o_divclk; +end + + +endmodule + |
