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authoruvok2026-01-09 15:18:23 +0100
committeruvok2026-01-09 15:18:23 +0100
commit6c83fd8730e55de8b1daaac1deb111d3d9bd408e (patch)
tree33a3dbc4fd87011b657b193224c3f39c5de6b766 /playground/debounce.v
parent678cb2d2d752bbac7625ba9b287762b3acabf116 (diff)
move stuff around
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+`timescale 1us/1us
+
+module debounce (
+ input rst_i,
+ input clk_i,
+ input signal_i,
+ output reg signal_o
+);
+
+// number of rising clock edges a signal needs to be stable
+// for it to be output.
+// (+1 for propagation).
+parameter STABLE_PERIOD = 50;
+parameter INIT_SIG_STATE = 1'b1;
+
+reg [31:0] clk_counter;
+reg prev_state;
+
+always @(posedge clk_i or negedge rst_i) begin
+ if (!rst_i) begin
+ // Learning: I would like to set the output to the input on reset
+ // but then I get
+ // Warning: Async reset value `\signal_i' is not constant!
+ // and a synthesis error.
+ clk_counter <= 0;
+ prev_state <= INIT_SIG_STATE;
+ signal_o <= INIT_SIG_STATE;
+ end else begin
+
+ if (signal_i != prev_state) begin
+ clk_counter <= 0;
+ prev_state <= signal_i;
+ end else begin
+ clk_counter <= clk_counter + 1;
+ end
+
+ if (clk_counter === STABLE_PERIOD) begin
+ signal_o <= signal_i;
+ end
+ end
+end
+
+// Learning?
+// Apparently, (and obviously, when you think about it),
+// it's not possible to drive a signal by two blocks
+// always @(signal_i) begin
+// if (signal_i != prev_state) begin
+// clk_counter <= 0;
+// prev_state <= signal_i;
+// end
+// end
+
+endmodule