(System)Verilog: Be explicit about wire/logic

1 files changed, 7 insertions, 7 deletions

diff --git a/playground/fifo.v b/playground/fifo.v
index bcc2d3f..a239069 100644
--- a/playground/fifo.v
+++ b/playground/fifo.v
@@ -6,18 +6,18 @@ module fifo #(
   parameter DATA_WIDTH = 8,
   parameter DATA_DEPTH = 1024
 ) (
-  input rst_i,
-  input clk_i,
+  input wire rst_i,
+  input wire clk_i,
 
-  input write_i,
-  input read_i,
+  input wire write_i,
+  input wire read_i,
 
-  output empty_o,
-  output full_o,
+  output wire empty_o,
+  output wire full_o,
 
   //output data_valid_o,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
+  input wire [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o
 
 );