(System)Verilog: Be explicit about wire/logic

1 files changed, 3 insertions, 3 deletions

diff --git a/playground/led_toggle_nonwork.v b/playground/led_toggle_nonwork.v
index 5fe458f..2450ce4 100644
--- a/playground/led_toggle_nonwork.v
+++ b/playground/led_toggle_nonwork.v
@@ -7,9 +7,9 @@
 //
 
 module led_toggle_nonwork(
-  input clk_i,
-  input key_i,
-  input rst_i,
+  input wire clk_i,
+  input wire key_i,
+  input wire rst_i,
   output reg [5:0] led
 );