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authoruvok2026-01-10 17:11:55 +0100
committeruvok2026-01-10 20:34:37 +0100
commit05cf070db62bfdaff99292660105159bd0367a66 (patch)
tree8b8debfbea90f8c19f99661ce065ad763a3150d5 /playground/my_mem.v
parent7d7ce2586c2a769259340c7e84f97eb3fd5b4b3e (diff)
Remove rando int
Diffstat (limited to 'playground/my_mem.v')
-rw-r--r--playground/my_mem.v24
1 files changed, 12 insertions, 12 deletions
diff --git a/playground/my_mem.v b/playground/my_mem.v
index c38db3a..ebffcb8 100644
--- a/playground/my_mem.v
+++ b/playground/my_mem.v
@@ -22,18 +22,18 @@ module my_mem #(
reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;
-`ifdef VERILATE
-initial begin
- r_datastore[0] = 'h11;
- r_datastore[1] = 'h22;
- r_datastore[2] = 'h33;
- r_datastore[3] = 'h44;
- r_datastore[4] = 'h55;
- r_datastore[5] = 'h66;
- r_datastore[6] = 'h77;
- r_datastore[7] = 'h88;
-end
-`endif
+// `ifdef VERILATE
+// initial begin
+// r_datastore[0] = 'h11;
+// r_datastore[1] = 'h22;
+// r_datastore[2] = 'h33;
+// r_datastore[3] = 'h44;
+// r_datastore[4] = 'h55;
+// r_datastore[5] = 'h66;
+// r_datastore[6] = 'h77;
+// r_datastore[7] = 'h88;
+// end
+// `endif
`ifdef DEBUG
// for debugging simulations, as iverilog