(System)Verilog: Be explicit about wire/logic

1 files changed, 7 insertions, 7 deletions

diff --git a/playground/my_mem.v b/playground/my_mem.v
index ebffcb8..b472c1e 100644
--- a/playground/my_mem.v
+++ b/playground/my_mem.v
@@ -7,17 +7,17 @@ module my_mem #(
   parameter DATA_WIDTH = 8,
   parameter DATA_DEPTH = 1024
 ) (
-  input clk_i,
+  input wire clk_i,
 
-  input write_en_i,
-  input read_en_i,
+  input wire write_en_i,
+  input wire read_en_i,
 
-  input [$clog2(DATA_DEPTH)-1:0] r_read_addr,
-  input [$clog2(DATA_DEPTH)-1:0] r_write_addr,
+  input wire [$clog2(DATA_DEPTH)-1:0] r_read_addr,
+  input wire [$clog2(DATA_DEPTH)-1:0] r_write_addr,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
+  input wire [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o,
-  output [(DATA_WIDTH-1) : 0] async_data_o
+  output wire [(DATA_WIDTH-1) : 0] async_data_o
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;