(System)Verilog: Be explicit about wire/logic

1 files changed, 5 insertions, 5 deletions

diff --git a/playground/par_to_ser.v b/playground/par_to_ser.v
index ab754c9..677f70b 100644
--- a/playground/par_to_ser.v
+++ b/playground/par_to_ser.v
@@ -5,12 +5,12 @@
 module par_to_ser #(
   parameter SHIFT_WIDTH = 8
 ) (
-  input rst_i,
-  input clk_i,
-  input data_valid_i,
-  input [(SHIFT_WIDTH-1):0] dat_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire data_valid_i,
+  input wire [(SHIFT_WIDTH-1):0] dat_i,
   output reg dat_o,
-  output dat_valid_o
+  output wire dat_valid_o
 );
 
 // Learning: can't declate parameter here