(System)Verilog: Be explicit about wire/logic

1 files changed, 6 insertions, 6 deletions

diff --git a/playground/ser_to_par.v b/playground/ser_to_par.v
index f0a0c47..edb05df 100644
--- a/playground/ser_to_par.v
+++ b/playground/ser_to_par.v
@@ -10,15 +10,15 @@
 module ser_to_par #(
   parameter SHIFT_WIDTH = 8
 ) (
-  input rst_i,
-  input clk_i,
+  input wire rst_i,
+  input wire clk_i,
 
-  input dat_valid_i,
-  input dat_i,
+  input wire dat_valid_i,
+  input wire dat_i,
 
-  output reg[(SHIFT_WIDTH - 1):0] dat_o,
+  output reg [(SHIFT_WIDTH - 1):0] dat_o,
   // ???
-  output dat_valid_o
+  output wire dat_valid_o
 );
 
 reg [$clog2(SHIFT_WIDTH) - 1 : 0] count = {$clog2(SHIFT_WIDTH){1'b0}};