(System)Verilog: Be explicit about wire/logic

13 files changed, 51 insertions, 51 deletions

diff --git a/playground/clkdiv.v b/playground/clkdiv.v
index b6f1419..442ff35 100644
--- a/playground/clkdiv.v
+++ b/playground/clkdiv.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module clkdiv (
-    input rst_i,
-    input clk,              // clk input
+    input wire rst_i,
+    input wire clk,              // clk input
     output reg o_divclk     // divided output (must be a reg, b/c it needs to keep state)
 );
 
diff --git a/playground/debounce.v b/playground/debounce.v
index 33dc22e..4c68e2e 100644
--- a/playground/debounce.v
+++ b/playground/debounce.v
@@ -1,9 +1,9 @@
 `timescale 1us/1us
 
 module debounce (
-  input rst_i,
-  input clk_i,
-  input signal_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire signal_i,
   output reg signal_o
 );
 
diff --git a/playground/fifo.v b/playground/fifo.v
index bcc2d3f..a239069 100644
--- a/playground/fifo.v
+++ b/playground/fifo.v
@@ -6,18 +6,18 @@ module fifo #(
   parameter DATA_WIDTH = 8,
   parameter DATA_DEPTH = 1024
 ) (
-  input rst_i,
-  input clk_i,
+  input wire rst_i,
+  input wire clk_i,
 
-  input write_i,
-  input read_i,
+  input wire write_i,
+  input wire read_i,
 
-  output empty_o,
-  output full_o,
+  output wire empty_o,
+  output wire full_o,
 
   //output data_valid_o,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
+  input wire [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o
 
 );
diff --git a/playground/fizzbuzz.v b/playground/fizzbuzz.v
index 0e34c58..d251198 100644
--- a/playground/fizzbuzz.v
+++ b/playground/fizzbuzz.v
@@ -1,11 +1,11 @@
 `timescale 1us/1us
 
 module fizzbuzz (
-  input [7:0] num_i,
-  output [7:0] num_o,
-  output fizz_o,
-  output buzz_o,
-  output fizzbuzz_o
+  input wire [7:0] num_i,
+  output wire [7:0] num_o,
+  output wire fizz_o,
+  output wire buzz_o,
+  output wire fizzbuzz_o
 );
 
 wire is_fizz, is_buzz;
diff --git a/playground/led.v b/playground/led.v
index e4f4281..bf402d2 100644
--- a/playground/led.v
+++ b/playground/led.v
@@ -3,8 +3,8 @@
 `include "clkdiv.v"
 
 module led (
-    input clk,              // clk input
-    input rst_i,              // reset input
+    input wire clk,              // clk input
+    input wire rst_i,              // reset input
     output reg [5:0] led_o    // 6 LEDS pin
 );
 
diff --git a/playground/led_toggle.v b/playground/led_toggle.v
index 3c54ee4..f26d3be 100644
--- a/playground/led_toggle.v
+++ b/playground/led_toggle.v
@@ -7,10 +7,10 @@
 `include "debounce.v"
 
 module led_toggle (
-  input rst_i,
-  input clk_i,
-  input key_i,
-  output [5:0] led
+  input wire rst_i,
+  input wire clk_i,
+  input wire key_i,
+  output wire [5:0] led
 );
 parameter STABLE_PERIOD = 50;
 
diff --git a/playground/led_toggle_bouncy.v b/playground/led_toggle_bouncy.v
index b05b472..8e783f2 100644
--- a/playground/led_toggle_bouncy.v
+++ b/playground/led_toggle_bouncy.v
@@ -4,9 +4,9 @@
 // bouncy variant
 
 module led_toggle_bouncy (
-  input clk_i,
-  input key_i,
-  output [5:0] led
+  input wire clk_i,
+  input wire key_i,
+  output wire [5:0] led
 );
 
 reg r_LED_1 = 1'b1;
diff --git a/playground/led_toggle_nonwork.v b/playground/led_toggle_nonwork.v
index 5fe458f..2450ce4 100644
--- a/playground/led_toggle_nonwork.v
+++ b/playground/led_toggle_nonwork.v
@@ -7,9 +7,9 @@
 //
 
 module led_toggle_nonwork(
-  input clk_i,
-  input key_i,
-  input rst_i,
+  input wire clk_i,
+  input wire key_i,
+  input wire rst_i,
   output reg [5:0] led
 );
 
diff --git a/playground/my_mem.v b/playground/my_mem.v
index ebffcb8..b472c1e 100644
--- a/playground/my_mem.v
+++ b/playground/my_mem.v
@@ -7,17 +7,17 @@ module my_mem #(
   parameter DATA_WIDTH = 8,
   parameter DATA_DEPTH = 1024
 ) (
-  input clk_i,
+  input wire clk_i,
 
-  input write_en_i,
-  input read_en_i,
+  input wire write_en_i,
+  input wire read_en_i,
 
-  input [$clog2(DATA_DEPTH)-1:0] r_read_addr,
-  input [$clog2(DATA_DEPTH)-1:0] r_write_addr,
+  input wire [$clog2(DATA_DEPTH)-1:0] r_read_addr,
+  input wire [$clog2(DATA_DEPTH)-1:0] r_write_addr,
 
-  input [(DATA_WIDTH-1) : 0] data_i,
+  input wire [(DATA_WIDTH-1) : 0] data_i,
   output reg [(DATA_WIDTH-1) : 0] data_o,
-  output [(DATA_WIDTH-1) : 0] async_data_o
+  output wire [(DATA_WIDTH-1) : 0] async_data_o
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */;
diff --git a/playground/par_to_ser.v b/playground/par_to_ser.v
index ab754c9..677f70b 100644
--- a/playground/par_to_ser.v
+++ b/playground/par_to_ser.v
@@ -5,12 +5,12 @@
 module par_to_ser #(
   parameter SHIFT_WIDTH = 8
 ) (
-  input rst_i,
-  input clk_i,
-  input data_valid_i,
-  input [(SHIFT_WIDTH-1):0] dat_i,
+  input wire rst_i,
+  input wire clk_i,
+  input wire data_valid_i,
+  input wire [(SHIFT_WIDTH-1):0] dat_i,
   output reg dat_o,
-  output dat_valid_o
+  output wire dat_valid_o
 );
 
 // Learning: can't declate parameter here
diff --git a/playground/ser_to_par.v b/playground/ser_to_par.v
index f0a0c47..edb05df 100644
--- a/playground/ser_to_par.v
+++ b/playground/ser_to_par.v
@@ -10,15 +10,15 @@
 module ser_to_par #(
   parameter SHIFT_WIDTH = 8
 ) (
-  input rst_i,
-  input clk_i,
+  input wire rst_i,
+  input wire clk_i,
 
-  input dat_valid_i,
-  input dat_i,
+  input wire dat_valid_i,
+  input wire dat_i,
 
-  output reg[(SHIFT_WIDTH - 1):0] dat_o,
+  output reg [(SHIFT_WIDTH - 1):0] dat_o,
   // ???
-  output dat_valid_o
+  output wire dat_valid_o
 );
 
 reg [$clog2(SHIFT_WIDTH) - 1 : 0] count = {$clog2(SHIFT_WIDTH){1'b0}};
diff --git a/playground/template.v b/playground/template.v
index e6f5280..2cbe671 100644
--- a/playground/template.v
+++ b/playground/template.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module template (
-  input rst_i,
-  input clk_i
+  input wire rst_i,
+  input wire clk_i
 );
 
 always @(posedge clk_i or negedge rst_i) begin
diff --git a/playground/tst_delay.v b/playground/tst_delay.v
index c4017bd..6d2c420 100644
--- a/playground/tst_delay.v
+++ b/playground/tst_delay.v
@@ -1,8 +1,8 @@
 `timescale 1us/1us
 
 module tst_delay (
-  input clk_i,
-  input data_i,
+  input wire clk_i,
+  input wire data_i,
   output reg data_o
 );