s2p: Fix testbench

needed data valid signal

1 files changed, 25 insertions, 17 deletions

diff --git a/ser_to_par.tb.v b/ser_to_par.tb.v
index ffa4172..de730c6 100644
--- a/ser_to_par.tb.v
+++ b/ser_to_par.tb.v
@@ -3,16 +3,19 @@
 module ser_to_par_tb (
 );
 
-reg clk_i;
-reg rst_i;
-reg dat_i;
-wire [7:0] dat_o;
+logic clk_i;
+logic rst_i;
+logic dat_i;
+logic dat_valid;
+logic [7:0] dat_o;
 
 ser_to_par uut(
   .clk_i(clk_i),
   .rst_i(rst_i),
   .dat_i(dat_i),
-  .dat_o(dat_o)
+  .dat_o(dat_o),
+  .dat_valid_i(dat_valid),
+  .dat_valid_o()
 );
 
 string filename;
@@ -23,32 +26,37 @@ initial begin
   filename="ser_to_par.lxt2";
 `endif
   $dumpfile(filename); $dumpvars();
-  clk_i <= 0;
-  rst_i <= 1'b1;
-  dat_i <= 1'b1;
+  clk_i = 0;
+  rst_i = 1'b1;
+  dat_i = 1'b1;
+  dat_valid= 1'b0;
   #1
-  rst_i <= 0;
+  rst_i = 0;
   #1
-  rst_i <= 1;
+  rst_i = 1;
 end
 
 always #10 clk_i = ~clk_i;
 
 initial begin
-  #37
+  #13;
+  @(negedge clk_i);
 
+  dat_valid = 1'b1;
   // start data
-  dat_i <= 1'b0;
-  #20
-
+  dat_i = 1'b0;
+  @(negedge clk_i);
   // - 1 clk cycle, 1 bit later:
-  dat_i <= 1'b1;
+  dat_i = 1'b1;
+
+  repeat (7) @(negedge clk_i);
+  dat_valid = 1'b0;
 
-  #140
   // - 7 clk cycle, 7 bits later:
   assert (dat_o == 8'hfe)
+  else $error("Excected dat_o to be hfe, was h%x", dat_o);
 
-  #20
+  @(negedge clk_i);
   $finish();
 end