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authoruvok2025-12-26 18:08:19 +0100
committeruvok2025-12-26 18:08:19 +0100
commit853bc8e1b782af25e95bf3582cf5069eec6e67d4 (patch)
tree2cd649674b6670e9d44e9b4e30939edce20ca8d6 /ser_to_par.v
parent46b791ab14a2624e17c4e24c86691d9b4a3ff64e (diff)
Complain about timing
Diffstat (limited to 'ser_to_par.v')
-rw-r--r--ser_to_par.v5
1 files changed, 5 insertions, 0 deletions
diff --git a/ser_to_par.v b/ser_to_par.v
index 754fdc0..d56dd03 100644
--- a/ser_to_par.v
+++ b/ser_to_par.v
@@ -11,6 +11,11 @@ module ser_to_par (
output reg[7:0] dat_o
);
+// Learning:
+// Ugh, this is fucking stupid.
+// if I send out directly at the rising clock edge,
+// the output will violate setup and hold times???
+//
always @(posedge clk_i or negedge rst_i) begin
if (!rst_i) begin
dat_o <= 8'b0;