diff options
| author | uvok | 2026-01-09 15:18:23 +0100 |
|---|---|---|
| committer | uvok | 2026-01-09 15:18:23 +0100 |
| commit | 6c83fd8730e55de8b1daaac1deb111d3d9bd408e (patch) | |
| tree | 33a3dbc4fd87011b657b193224c3f39c5de6b766 /tst_delay_tb.v | |
| parent | 678cb2d2d752bbac7625ba9b287762b3acabf116 (diff) | |
move stuff around
Diffstat (limited to 'tst_delay_tb.v')
| -rw-r--r-- | tst_delay_tb.v | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/tst_delay_tb.v b/tst_delay_tb.v deleted file mode 100644 index 5812068..0000000 --- a/tst_delay_tb.v +++ /dev/null @@ -1,53 +0,0 @@ -// try to figure out how iverilog samples edges -`timescale 1us/1us - -module tst_delay_tb; - -reg clk_i; -reg data_i; -wire data_o; - -tst_delay uut ( - .clk_i(clk_i), - .data_i(data_i), - .data_o(data_o) -); - -string filename; -initial begin -`ifdef DUMP_FILE_NAME - filename=`DUMP_FILE_NAME; -`else - filename="tst_delay.lxt2"; -`endif - $dumpfile(filename); $dumpvars(); - clk_i = 0; - data_i = 0; -end - -always #10 clk_i = ~clk_i; - -initial begin - #9 - data_i = 1; - #2 - data_i = 0; - - /* verilator lint_off INITIALDLY */ - // note the <= assignment - #19 - data_i <= 1; - /* verilator lint_on INITIALDLY */ - - #1 - data_i = 0; - // note the = assignment - #19 - data_i = 1; - #1 - data_i = 0; - #40 - $finish(); -end - -endmodule |
