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authoruvok2025-12-30 10:21:27 +0100
committeruvok2025-12-30 10:21:27 +0100
commitd0a372c3112b28ff3b1bf03ff4a7a0e5a3cafe8e (patch)
tree633ac83187da0a244d081e124d4cfba5c2b712c1 /tst_delay_tb.v
parent613e0e72128d7745ab084f2f703984e154c75d67 (diff)
linting, use different naming
use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match
Diffstat (limited to 'tst_delay_tb.v')
-rw-r--r--tst_delay_tb.v54
1 files changed, 54 insertions, 0 deletions
diff --git a/tst_delay_tb.v b/tst_delay_tb.v
new file mode 100644
index 0000000..03ef185
--- /dev/null
+++ b/tst_delay_tb.v
@@ -0,0 +1,54 @@
+// try to figure out how iverilog samples edges
+`timescale 1us/1us
+
+module tst_delay_tb (
+);
+
+reg clk_i;
+reg data_i;
+wire data_o;
+
+tst_delay uut (
+ .clk_i(clk_i),
+ .data_i(data_i),
+ .data_o(data_o)
+);
+
+string filename;
+initial begin
+`ifdef DUMP_FILE_NAME
+ filename=`DUMP_FILE_NAME;
+`else
+ filename="tst_delay.lxt2";
+`endif
+ $dumpfile(filename); $dumpvars();
+ clk_i = 0;
+ data_i = 0;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+ #9
+ data_i = 1;
+ #2
+ data_i = 0;
+
+ /* verilator lint_off INITIALDLY */
+ // note the <= assignment
+ #19
+ data_i <= 1;
+ /* verilator lint_on INITIALDLY */
+
+ #1
+ data_i = 0;
+ // note the = assignment
+ #19
+ data_i = 1;
+ #1
+ data_i = 0;
+ #40
+ $finish();
+end
+
+endmodule