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| -rw-r--r-- | README.txt | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -3,4 +3,4 @@ Learnings: - Anything that needs to "store" a state must be a reg? => wire's can't be assigned in always blocks, yosys complains - regs must not lead to wires? (unsure where I read that) - +- Clock on the tang9k is 27 MHz |
