diff options
| -rw-r--r-- | eater_cpu/eater_computer.sv | 11 | ||||
| -rw-r--r-- | eater_cpu/eater_computer_tb.sv | 83 | ||||
| -rw-r--r-- | eater_cpu/eater_decoder.sv | 7 |
3 files changed, 51 insertions, 50 deletions
diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv index b93f289..7c8eb17 100644 --- a/eater_cpu/eater_computer.sv +++ b/eater_cpu/eater_computer.sv @@ -7,6 +7,8 @@ module eater_computer( // clock input input wire clk_in, + // Whether to automatically run (vs manual control) + input wire auto_run_in, // current content of the bus output wire [7:0] debug_bus ); @@ -40,7 +42,11 @@ wire [7:0] // PC is only 4 bit. wire [3:0] PC_in, PC_out; -CpuControlFlags flags; +CpuControlFlags manual_flags; +wire CpuControlFlags automatic_flags; +wire CpuControlFlags flags; + +assign flags = auto_run_in ? automatic_flags : manual_flags; /* verilator public_off */ @@ -161,8 +167,7 @@ eater_register OUT ( eater_decoder decoder ( .clk_i(clk_in), .instruction_i(INS_out), - .enable_control_i(0), - .flags_o() + .flags_o(automatic_flags) ); endmodule diff --git a/eater_cpu/eater_computer_tb.sv b/eater_cpu/eater_computer_tb.sv index 019bcb1..1104c9b 100644 --- a/eater_cpu/eater_computer_tb.sv +++ b/eater_cpu/eater_computer_tb.sv @@ -8,6 +8,7 @@ logic clk_in; eater_computer uut ( .debug_bus(), + .auto_run_in(1'b0), .clk_in(clk_in) ); @@ -24,20 +25,20 @@ initial begin $dumpfile("simpc.vvp"); $dumpvars(); - uut.flags.A_out = 0; - uut.flags.B_out = 0; - uut.flags.INS_out = 0; - uut.flags.ALU_out = 0; - uut.flags.RAM_out = 0; - uut.flags.PC_out = 0; - uut.flags.PC_count = 0; - - uut.flags.A_in = 0; - uut.flags.B_in = 0; - uut.flags.INS_in = 0; - uut.flags.RAM_in = 0; - uut.flags.PC_in = 0; - uut.flags.MAR_in = 0; + uut.manual_flags.A_out = 0; + uut.manual_flags.B_out = 0; + uut.manual_flags.INS_out = 0; + uut.manual_flags.ALU_out = 0; + uut.manual_flags.RAM_out = 0; + uut.manual_flags.PC_out = 0; + uut.manual_flags.PC_count = 0; + + uut.manual_flags.A_in = 0; + uut.manual_flags.B_in = 0; + uut.manual_flags.INS_in = 0; + uut.manual_flags.RAM_in = 0; + uut.manual_flags.PC_in = 0; + uut.manual_flags.MAR_in = 0; clk_in = 0; debug_enable = 0; debug_value = 'z; @@ -52,91 +53,91 @@ initial begin @(negedge clk_in); debug_value = 'h00; - uut.flags.MAR_in = 1; + uut.manual_flags.MAR_in = 1; @(negedge clk_in); - uut.flags.MAR_in = 0; + uut.manual_flags.MAR_in = 0; debug_value = 'h04; - uut.flags.PC_in = 1; + uut.manual_flags.PC_in = 1; @(negedge clk_in); - uut.flags.PC_in = 0; + uut.manual_flags.PC_in = 0; debug_value = 'haa; - uut.flags.A_in = 1; + uut.manual_flags.A_in = 1; @(negedge clk_in); - uut.flags.A_in = 0; + uut.manual_flags.A_in = 0; debug_value = 'hbb; - uut.flags.B_in = 1; + uut.manual_flags.B_in = 1; @(negedge clk_in); - uut.flags.B_in = 0; + uut.manual_flags.B_in = 0; debug_value = 'hcc; - uut.flags.INS_in = 1; + uut.manual_flags.INS_in = 1; @(negedge clk_in); - uut.flags.INS_in = 0; + uut.manual_flags.INS_in = 0; debug_value = 'hdd; - uut.flags.RAM_in = 1; + uut.manual_flags.RAM_in = 1; @(negedge clk_in); - uut.flags.RAM_in = 0; + uut.manual_flags.RAM_in = 0; @(negedge clk_in); debug_enable = 0; debug_value = 'z; @(negedge clk_in); - uut.flags.A_out = 1; + uut.manual_flags.A_out = 1; @(negedge clk_in); assert (uut.bus == 'haa) else $error("Expected 0xaa (from REG A), got 0x%02x on bus", uut.bus); - uut.flags.A_out = 0; - uut.flags.B_out = 1; + uut.manual_flags.A_out = 0; + uut.manual_flags.B_out = 1; @(negedge clk_in); assert (uut.bus == 'hbb) else $error("Expected 0xbb (from REG B), got 0x%02x on bus", uut.bus); - uut.flags.B_out = 0; - uut.flags.INS_out = 1; + uut.manual_flags.B_out = 0; + uut.manual_flags.INS_out = 1; @(negedge clk_in); assert (uut.bus == 'h0c) else $error("Expected 0x0c (from INS), got 0x%02x on bus", uut.bus); // ERROR: TODO: should I expect 'zc or '0c ? - uut.flags.INS_out = 0; + uut.manual_flags.INS_out = 0; @(negedge clk_in); - uut.flags.ALU_out = 1; + uut.manual_flags.ALU_out = 1; @(negedge clk_in); assert (uut.bus == 8'('haa + 'hbb)) else $error("Expected 0x%02x (from ALU), got 0x%02x on bus", 8'('haa + 'hbb), uut.bus); - uut.flags.ALU_out = 0; - uut.flags.PC_out = 1; + uut.manual_flags.ALU_out = 0; + uut.manual_flags.PC_out = 1; @(negedge clk_in); assert (uut.bus == 'h04) else $error("Expected 0x04 (from PC), got 0x%02x on bus", uut.bus); - uut.flags.PC_out = 0; - uut.flags.RAM_out = 1; + uut.manual_flags.PC_out = 0; + uut.manual_flags.RAM_out = 1; @(negedge clk_in); assert (uut.bus == 'hdd) else $error("Expected 0xdd (from RAM), got 0x%02x on bus", uut.bus); - uut.flags.RAM_out = 0; + uut.manual_flags.RAM_out = 0; @(negedge clk_in); debug_enable = 1; debug_value = 'h01; - uut.flags.MAR_in = 1; + uut.manual_flags.MAR_in = 1; @(negedge clk_in); debug_enable = 0; debug_value = 'bz; - uut.flags.MAR_in = 0; - uut.flags.RAM_out = 1; + uut.manual_flags.MAR_in = 0; + uut.manual_flags.RAM_out = 1; @(negedge clk_in); $info("Got 0x%02x from RAM", uut.bus); diff --git a/eater_cpu/eater_decoder.sv b/eater_cpu/eater_decoder.sv index 1ce9cee..2246826 100644 --- a/eater_cpu/eater_decoder.sv +++ b/eater_cpu/eater_decoder.sv @@ -4,7 +4,6 @@ module eater_decoder ( input clk_i, - input wire enable_control_i, input wire [7:0] instruction_i, output CpuControlFlags flags_o ); @@ -13,11 +12,7 @@ CpuState internal_state; CpuState next_state; CpuControlFlags internal_flags; -always_comb begin - if (enable_control_i) begin - flags_o = internal_flags; - end -end +assign flags_o = internal_flags; initial begin internal_state = INIT; |