diff options
| -rw-r--r-- | eater_cpu/eater_alu.sv | 5 | ||||
| -rw-r--r-- | eater_cpu/eater_computer.sv | 15 | ||||
| -rw-r--r-- | eater_cpu/eater_types.sv | 6 |
3 files changed, 24 insertions, 2 deletions
diff --git a/eater_cpu/eater_alu.sv b/eater_cpu/eater_alu.sv index b1ed7ea..d8748a4 100644 --- a/eater_cpu/eater_alu.sv +++ b/eater_cpu/eater_alu.sv @@ -2,6 +2,8 @@ `timescale 1us/1us +`include "eater_types.sv" + module eater_alu ( input wire clk_in, input wire en_output_in, @@ -11,7 +13,8 @@ module eater_alu ( input wire [7:0] A_in, input wire [7:0] B_in, - output wire [7:0] bus_out + output wire [7:0] bus_out, + output wire AluFlags flags_out ); wire [7:0] result /* verilator public */; diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv index 75a54c9..b22096a 100644 --- a/eater_cpu/eater_computer.sv +++ b/eater_cpu/eater_computer.sv @@ -41,6 +41,9 @@ wire [7:0] OUT_out ; +// ALU flags. int: direct out. out: buffered output (for decoder). +wire AluFlags ALU_flags_int, ALU_flags_out; + // PC is only 4 bit. wire [3:0] PC_in, PC_out; @@ -134,7 +137,8 @@ eater_alu alu ( .A_in(A_out), .B_in(B_out), .subtract_n_add_in(flags.ALU_subtract_nadd), - .bus_out(bus) + .bus_out(bus), + .flags_out(ALU_flags_int) ); assign PC_in = bus[3:0]; @@ -167,6 +171,15 @@ eater_register OUT_reg ( .always_out(OUT_out) ); +eater_register ALU_flags ( + .clk_in(clk_in), + .en_store_in(flags.flags_in), + .en_output_in(1'b0), + .data_in(ALU_flags_int), + .bus_out(), + .always_out(ALU_flags_out) +); + // run decoder on negated clock, // allowing stuff to be clocked in "early" wire DEC_clk_neg = ~clk_in; diff --git a/eater_cpu/eater_types.sv b/eater_cpu/eater_types.sv index b0e5592..3744df1 100644 --- a/eater_cpu/eater_types.sv +++ b/eater_cpu/eater_types.sv @@ -73,6 +73,12 @@ typedef enum logic[3:0] { HALT_op = 'b1111 } eater_instruction; +typedef struct packed { + logic Zero; + logic Carry; + logic [5:0] reserved; +} AluFlags; + // CPU control flags `ifdef IVERILOG typedef struct packed { |