4 files changed, 134 insertions, 0 deletions
diff --git a/par_to_ser.tb.v b/par_to_ser.tb.v
new file mode 100644
index 0000000..ad3f7c0
--- /dev/null
+++ b/par_to_ser.tb.v
@@ -0,0 +1,43 @@
+`timescale 1us/1ns
+
+module par_to_ser_tb (
+);
+
+reg clk_i;
+reg rst_i;
+reg do_send_i;
+reg [7:0] dat_i;
+wire dat_o;
+
+par_to_ser uut(
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .do_send_i(do_send_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o)
+);
+
+initial begin
+  $dumpfile("par_to_ser.lxt2"); $dumpvars();
+  clk_i <= 0;
+  rst_i <= 1'b1;
+  do_send_i <= 1'b0;
+
+  #1
+  rst_i <= 1'b0;
+  #1
+  rst_i <= 1'b1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #37
+  dat_i <= 8'haa;
+  #13
+  do_send_i <= 1'b1;
+  #600
+  $finish();
+end
+
+endmodule
diff --git a/par_to_ser.v b/par_to_ser.v
new file mode 100644
index 0000000..a71abec
--- /dev/null
+++ b/par_to_ser.v
@@ -0,0 +1,32 @@
+// parallel to serial converter
+// Learning:
+// I think I need a "start" signal (do_send_i),
+// otherwise I'll never know when to copy the input data
+// to out internal register
+
+module par_to_ser (
+  input rst_i,
+  input clk_i,
+  input do_send_i,
+  input [7:0] dat_i,
+  output reg dat_o
+);
+
+reg sending = 1'b0;
+reg [7:0] send_data = 8'hff;
+
+always @(posedge clk_i or negedge rst_i) begin
+  if (!rst_i) begin
+    dat_o <= 1'b1;
+  end else if (do_send_i && !sending) begin
+    sending <= 1;
+    send_data <= dat_i;
+  end else if (sending) begin
+    dat_o = send_data[0];
+    send_data[6:0] <= send_data[7:1];
+    // arbitrary decision: register is filled with a 1
+    send_data[7] = 1'b1;
+  end
+end
+
+endmodule
diff --git a/ser_to_par.tb.v b/ser_to_par.tb.v
new file mode 100644
index 0000000..c86edfa
--- /dev/null
+++ b/ser_to_par.tb.v
@@ -0,0 +1,36 @@
+`timescale 1us/1ns
+
+module ser_to_par_tb (
+);
+
+reg clk_i;
+reg rst_i;
+reg dat_i;
+wire [7:0] dat_o;
+
+ser_to_par uut(
+  .clk_i(clk_i),
+  .rst_i(rst_i),
+  .dat_i(dat_i),
+  .dat_o(dat_o)
+);
+
+initial begin
+  $dumpfile("ser_to_par.lxt2"); $dumpvars();
+  clk_i <= 0;
+  rst_i <= 1'b1;
+  dat_i <= 1'b1;
+  #1
+  rst_i <= 0;
+  #1
+  rst_i <= 1;
+end
+
+always #10 clk_i = ~clk_i;
+
+initial begin
+  #400
+  $finish();
+end
+
+endmodule
diff --git a/ser_to_par.v b/ser_to_par.v
new file mode 100644
index 0000000..754fdc0
--- /dev/null
+++ b/ser_to_par.v
@@ -0,0 +1,23 @@
+// serial to parallel converter
+// Learning:
+// I don't like this.
+// I think I need a signal / way to say "I'm finished"?
+//
+
+module ser_to_par (
+  input rst_i,
+  input clk_i,
+  input dat_i,
+  output reg[7:0] dat_o
+);
+
+always @(posedge clk_i or negedge rst_i) begin
+  if (!rst_i) begin
+    dat_o <= 8'b0;
+  end else begin
+    dat_o[0] <= dat_i;
+    dat_o[7:1] <= dat_o[6:0];
+  end
+end
+
+endmodule