diff options
| -rw-r--r-- | nandgame/comb_mem.sv | 4 | ||||
| -rw-r--r-- | nandgame/logic_unit.sv | 3 | ||||
| -rw-r--r-- | nandgame/nandgame_types.v | 8 |
3 files changed, 15 insertions, 0 deletions
diff --git a/nandgame/comb_mem.sv b/nandgame/comb_mem.sv index bbfdcd0..dcda331 100644 --- a/nandgame/comb_mem.sv +++ b/nandgame/comb_mem.sv @@ -1,3 +1,7 @@ +// nandgame "combined memory" +// contains registers A, D and *A result +// located in memory. + `timescale 1us/1us `include "../my_mem.v" diff --git a/nandgame/logic_unit.sv b/nandgame/logic_unit.sv index 32b9691..93cb399 100644 --- a/nandgame/logic_unit.sv +++ b/nandgame/logic_unit.sv @@ -14,11 +14,14 @@ module logic_unit #( output logic [(DATA_WIDTH-1):0] RES ); +// learning: instead of this nested ternary... // assign RES = operation == LOGIC_AND ? (X & Y) : // operation == LOGIC_OR ? (X | Y) : // operation == LOGIC_XOR ? (X ^ Y) : // operation == LOGIC_NEGT ? (~X) : 0; +// ... you can do this: + always_comb begin case (operation) LOGIC_AND: RES = X & Y; diff --git a/nandgame/nandgame_types.v b/nandgame/nandgame_types.v index f7273da..2558383 100644 --- a/nandgame/nandgame_types.v +++ b/nandgame/nandgame_types.v @@ -1,3 +1,11 @@ +// common types for nandgame + +// learning: +// you need an include guard if you include files +// in multiple files. +// otherwise, iverilog and verilator will +// complain when loading the test bench and the +// corresponding uut. `ifndef NANDGAME_TYPES_SV `define NANDGAME_TYPES_SV |