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| -rw-r--r-- | debounce.v | 4 |
1 files changed, 4 insertions, 0 deletions
@@ -16,6 +16,10 @@ reg prev_state; always @(posedge clk_i or negedge rst_i) begin if (!rst_i) begin + // Learning: I would like to set the output to the input on reset + // but then I get + // Warning: Async reset value `\signal_i' is not constant! + // and a synthesis error. clk_counter <= 0; prev_state <= INIT_SIG_STATE; signal_o <= INIT_SIG_STATE; |
