diff options
| -rw-r--r-- | fifo.v | 10 |
1 files changed, 8 insertions, 2 deletions
@@ -36,18 +36,24 @@ always @(posedge clk_i or negedge rst_i) begin r_read_addr <= 0; r_write_addr <= 0; end else if (write_i && read_i) begin + r_count <= r_count + 1; + r_datastore[r_write_addr] <= data_i; // nothing to do end else if (write_i && !full_o) begin r_count <= r_count + 1; r_datastore[r_write_addr] <= data_i; + end else if (read_i && !empty_o) begin + r_count <= r_count - 1; + end + + if (!rst_i) begin + end else if (write_i && !full_o) begin // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does? if ({1'b0, r_write_addr} < (DATA_DEPTH - 1)) r_write_addr <= r_write_addr + 1; else r_write_addr <= 0; end else if (read_i && !empty_o) begin - r_count <= r_count - 1; - data_o <= r_datastore[r_read_addr]; // the_verilator wrongly (???) assumes DATA_DEPTH-1 requires 1 more bit than it does? if ({1'b0, r_read_addr} < (DATA_DEPTH - 1)) r_read_addr <= r_read_addr + 1; |
