diff options
| -rw-r--r-- | eater_cpu/eater_computer.sv | 54 |
1 files changed, 34 insertions, 20 deletions
diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv index b9863e8..1e618d1 100644 --- a/eater_cpu/eater_computer.sv +++ b/eater_cpu/eater_computer.sv @@ -2,11 +2,6 @@ `timescale 1us/1us -module eater_computer( - input wire clk_in, - output wire [7:0] debug_bus -); - // fucking being including so that VScode extensions find this module // (because config'ing the include path alone doesn't help) // vs fucking actually compiling it and tools complaining about the fucking timescale. @@ -14,6 +9,11 @@ module eater_computer( `include "../playground/my_mem.v" `endif +module eater_computer( + input wire clk_in, + output wire [7:0] debug_bus +); + /* verilator public_on */ tri [7:0] bus, A_out, B_out, RAM_out; logic A_to_bus, bus_to_A, @@ -23,21 +23,6 @@ logic A_to_bus, bus_to_A, ALU_to_bus ; -my_mem #( - .DATA_WIDTH(8), - .DATA_DEPTH(16) -) RAM ( - .clk_i(clk_in), - .write_en_i(bus_to_RAM), - // ??? - .read_en_i(RAM_to_bus), - .r_read_addr(), - .r_write_addr(), - .data_i(bus), - .data_o(), - .async_data_o(RAM_out) -); - assign bus = RAM_to_bus ? RAM_out : 8'bz; assign debug_bus = bus; @@ -76,6 +61,35 @@ eater_register INS ( // .data(ins_bus_out) ); +tri [7:0] mem_adr_bus_out; +tri [3:0] adr_RAM_in = mem_adr_bus_out[3:0]; + +eater_register MEM_ADR ( + .clk_in(clk_in), + .en_store_in(bus_to_INS), + .en_output_in(INS_to_bus), + .data_in(bus), + .bus_out(mem_adr_bus_out), + .always_out() + // .data(mem_adr_bus_out) +); + +// Eater RAM is sync??? +my_mem #( + .DATA_WIDTH(8), + .DATA_DEPTH(16) +) RAM ( + .clk_i(clk_in), + .write_en_i(bus_to_RAM), + // ??? + .read_en_i(RAM_to_bus), + .r_read_addr(adr_RAM_in), + .r_write_addr(adr_RAM_in), + .data_i(bus), + .data_o(), + .async_data_o(RAM_out) +); + eater_alu alu ( .clk_in(clk_in), .en_output_in(ALU_to_bus), |