diff options
| -rw-r--r-- | ser_to_par.v | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/ser_to_par.v b/ser_to_par.v index fc6d22f..0a8c4c4 100644 --- a/ser_to_par.v +++ b/ser_to_par.v @@ -5,25 +5,27 @@ // or generally, an enable pin. // -module ser_to_par ( +module ser_to_par #( + parameter SHIFT_WIDTH = 8 +) ( input rst_i, input clk_i, + + input dat_valid_i, input dat_i, - output reg[7:0] dat_o + + output reg[(SHIFT_WIDTH - 1):0] dat_o, + // ??? + output dat_valid_o ); -// Learning: -// Ugh, this is fucking stupid. -// if I send out directly at the rising clock edge, -// the output, when directly used again with the same clock, -// will violate setup and hold times??? -// always @(posedge clk_i or negedge rst_i) begin if (!rst_i) begin dat_o <= 8'b0; - end else begin - dat_o[7] <= dat_i; - dat_o[6:0] <= dat_o[7:1]; + end else if(dat_valid_i) begin + // shift into highest bit first, so it is subsequently shifted down + dat_o[SHIFT_WIDTH - 1] <= dat_i; + dat_o[(SHIFT_WIDTH - 2):0] <= dat_o[(SHIFT_WIDTH - 1):1]; end end |