2 files changed, 16 insertions, 33 deletions
diff --git a/fizzbuzz.tb.v b/fizzbuzz.tb.v
index 54095cc..7855a9b 100644
--- a/fizzbuzz.tb.v
+++ b/fizzbuzz.tb.v
@@ -4,20 +4,17 @@ module fizzbuzz_tb (
 );
 
 
-reg [7:0] number = 0;
-reg[2:0] fftst;
-wire [7:0] num_out;
-reg clk_i = 0;
+logic [7:0] number;
+logic clk_i;
+
+logic [7:0] num_out;
 
 fizzbuzz uut(
-  .clk_i(clk_i),
   .num_i(number),
   .num_o(num_out),
   .fizz_o(),
   .buzz_o(),
-  .fizzbuzz_o(),
-  // I still don't 100% get non-blocking assignments
-  .ff_test_o(fftst)
+  .fizzbuzz_o()
 );
 
 string filename;
@@ -29,19 +26,24 @@ initial begin
 `endif
   $dumpfile(filename); $dumpvars();
 
+
+  clk_i = 0;
+  number = '0;
 end
 
 always #10 begin
+  clk_i = ~clk_i;
+end
+
+always @(negedge clk_i) begin
   number <= number + 1;
-  clk_i <= ~clk_i;
+  // give iverilog some simulation time...
+  #1;
   if (number == 3) assert(num_out == 0);
   if (number == 5) assert(num_out == 0);
   if (number == 15) assert(num_out == 0);
-end
 
-initial begin
-  #2570
-  $finish();
+  if (number == 255) $finish;
 end
 
 endmodule
diff --git a/fizzbuzz.v b/fizzbuzz.v
index 9dd215f..0e34c58 100644
--- a/fizzbuzz.v
+++ b/fizzbuzz.v
@@ -1,13 +1,11 @@
 `timescale 1us/1us
 
 module fizzbuzz (
-  input clk_i,
   input [7:0] num_i,
   output [7:0] num_o,
   output fizz_o,
   output buzz_o,
-  output fizzbuzz_o,
-  output reg[2:0] ff_test_o
+  output fizzbuzz_o
 );
 
 wire is_fizz, is_buzz;
@@ -19,21 +17,4 @@ assign buzz_o = !is_fizz && is_buzz;
 assign fizzbuzz_o = is_fizz && is_buzz;
 assign num_o = (is_fizz || is_buzz) ? 0 : num_i;
 
-
-initial begin
-  ff_test_o = 0;
-end
-
-always @(posedge clk_i ) begin
-  if (num_i == 11)
-    ff_test_o <= 1;
-  else if (num_i == 13)
-    ff_test_o <= 2;
-  else if (num_i == 17)
-    ff_test_o <= 3;
-  else if (num_i == 23)
-    ff_test_o <= 4;
-  
-end
-
 endmodule