1 files changed, 7 insertions, 0 deletions
diff --git a/my_mem.v b/my_mem.v
index 68a96d0..99dd878 100644
--- a/my_mem.v
+++ b/my_mem.v
@@ -20,20 +20,27 @@ module my_mem #(
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0];
+
+`ifdef DEBUG
 // for debugging simulations, as iverilog
 // does't show r_datastore
 reg [(DATA_WIDTH-1) : 0] r_cur_r_val;
 reg [(DATA_WIDTH-1) : 0] r_cur_w_val;
+`endif
 
 always @(posedge clk_i) begin
   if (write_en_i) begin
     r_datastore[r_write_addr] <= data_i;
+`ifdef DEBUG
     r_cur_w_val <= data_i;
+`endif
   end
 
   if (read_en_i) begin
     data_o <= r_datastore[r_read_addr];
+`ifdef DEBUG
     r_cur_r_val <= r_datastore[r_read_addr];
+`endif
   end
 end