4 files changed, 38 insertions, 9 deletions
diff --git a/eater_cpu/eater_alu.sv b/eater_cpu/eater_alu.sv
index 1474d6d..39aa37d 100644
--- a/eater_cpu/eater_alu.sv
+++ b/eater_cpu/eater_alu.sv
@@ -19,6 +19,10 @@ wire [7:0] result = subtract_n_add_in ? (A_in - B_in) : (A_in + B_in);
 // wire [7:0] B_neg_if = B_in ^ xormask;
 // wire [7:0] result2 = A_in + B_neg_if + subtract_n_add_in;
 
-assign bus_out = en_output_in ? result : 8'bz;
-    
+zbuffer buffer (
+    .data_in(result),
+    .en_output_in(en_output_in),
+    .data_out(bus_out)
+);
+
 endmodule
diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index 4c59697..4f71f1c 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -21,7 +21,7 @@ logic A_to_bus, bus_to_A,
       INS_to_bus, bus_to_INS,
       RAM_to_bus, bus_to_RAM,
       ALU_to_bus,
-      PC_to_bus, bus_to_PC,
+      PC_to_bus, bus_to_PC, PC_count_en,
       bus_to_MAR
 ;
 
@@ -90,7 +90,11 @@ my_mem #(
   .async_data_o(RAM_out)
 );
 
-assign bus = RAM_to_bus ? RAM_out : 8'bz;
+zbuffer ram_to_bus_buffer (
+    .data_in(RAM_out),
+    .en_output_in(RAM_to_bus),
+    .data_out(bus)
+);
 
 eater_alu alu (
   .clk_in(clk_in),
@@ -108,11 +112,19 @@ counter #(
   .DATA_WIDTH(4)
 ) PC (
   .clk_in(clk_in),
-  .counter_out(PC_out),
   .X_in(PC_in),
-  .st_store_X_in(bus_to_PC)
+  .st_store_X_in(bus_to_PC),
+  .count_enable_in(PC_count_en),
+  .counter_out(PC_out)
 );
 
-assign bus[3:0] = PC_to_bus ? PC_out[3:0] : 4'bz;
+tri[7:0] PC_out_full;
+assign PC_out_full = {4'b0, PC_out};
+
+zbuffer PC_to_bus_buffer (
+    .data_in(PC_out_full),
+    .en_output_in(PC_to_bus),
+    .data_out(bus)
+);
 
 endmodule
diff --git a/eater_cpu/eater_computer_tb.sv b/eater_cpu/eater_computer_tb.sv
index 74ffb8a..5b14620 100644
--- a/eater_cpu/eater_computer_tb.sv
+++ b/eater_cpu/eater_computer_tb.sv
@@ -30,6 +30,8 @@ initial begin
   uut.ALU_to_bus = 0;
   uut.RAM_to_bus = 0;
   uut.PC_to_bus = 0;
+  uut.PC_count_en = 0;
+
   uut.bus_to_A = 0;
   uut.bus_to_B = 0;
   uut.bus_to_INS = 0;
@@ -79,6 +81,13 @@ initial begin
   @(negedge clk_in);
   assert (uut.bus == 8'('haa + 'hbb))
   else   $error("Expected 0x%02x, got 0x%02x on bus", 8'('haa + 'hbb), uut.bus);
+  uut.ALU_to_bus = 0;
+  uut.PC_to_bus = 1;
+
+  @(negedge clk_in);
+  assert (uut.bus == 'h00) 
+  else   $error("Expected 0x00, got 0x%02x on bus", uut.bus);
+  uut.PC_to_bus = 0;
 
   #10
   $finish();
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 2aded22..96fc205 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -30,9 +30,13 @@ always @(posedge clk_in) begin
   end
 end
 
-assign bus_out = en_output_in ? r_datastore : 8'bz;
+zbuffer buffer (
+  .data_in(r_datastore),
+  .en_output_in(en_output_in),
+  .data_out(bus_out)
+);
+
 assign always_out = r_datastore;
-// assign data = en_output_in ? r_datastore : 8'bz;
 
 endmodule