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| -rw-r--r-- | README.txt | 8 |
1 files changed, 7 insertions, 1 deletions
@@ -18,4 +18,10 @@ Questions: - Does yosys and other tools "automatically" determine the "perfect" wire/register (bus) width if I just specify e.g. wire BLA = 1374; - ?
\ No newline at end of file + ? +- The book tasked me with writing a serial-to-parallel and parallel-to-serial converter. + But I think I wrote it "wrong"? + If I used this in the real world, and chained both components together, + things would go wrong. as the output is flipped at the rising clock + edge - violating timings and leading to unpredictable behavior? + Or not? |