diff options
| -rw-r--r-- | my_mem.v | 2 | ||||
| -rw-r--r-- | nandgame/alu.sv | 4 | ||||
| -rw-r--r-- | nandgame/computer.sv | 16 |
3 files changed, 13 insertions, 9 deletions
@@ -19,7 +19,7 @@ module my_mem #( output reg [(DATA_WIDTH-1) : 0] data_o ); -reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0]; +reg [(DATA_WIDTH-1) : 0] r_datastore [(DATA_DEPTH-1) : 0] /* verilator public */; `ifdef DEBUG // for debugging simulations, as iverilog diff --git a/nandgame/alu.sv b/nandgame/alu.sv index f452d32..54297c9 100644 --- a/nandgame/alu.sv +++ b/nandgame/alu.sv @@ -29,8 +29,8 @@ module alu #( output logic [(DATA_WIDTH-1):0] result_out ); -logic [(DATA_WIDTH-1):0] int_op_x; -logic [(DATA_WIDTH-1):0] int_op_y; +logic [(DATA_WIDTH-1):0] int_op_x /* verilator public */; +logic [(DATA_WIDTH-1):0] int_op_y /* verilator public */; logic [(DATA_WIDTH-1):0] int_result_arith; logic [(DATA_WIDTH-1):0] int_result_logic; diff --git a/nandgame/computer.sv b/nandgame/computer.sv index 82b0c72..5f33698 100644 --- a/nandgame/computer.sv +++ b/nandgame/computer.sv @@ -14,8 +14,8 @@ module computer ( wire nclk_int; assign nclk_int = ~clk_in; -logic [15:0] PC_addr_int; -logic [15:0] PC_content_int; +logic [15:0] PC_addr_int /* verilator public */; +logic [15:0] PC_content_int /* verilator public */; my_mem #( .DATA_WIDTH(16), @@ -30,9 +30,13 @@ my_mem #( .data_o(PC_content_int) ); -logic [15:0] reg_A_int, reg_D_int, reg_pA_int; -logic store_to_A_int, store_to_D_int, store_to_pA_int; -logic [15:0] result_int; +logic [15:0] reg_A_int /* verilator public */, + reg_D_int /* verilator public */, + reg_pA_int /* verilator public */; +logic store_to_A_int /* verilator public */, + store_to_D_int /* verilator public */, + store_to_pA_int /* verilator public */; +logic [15:0] result_int /* verilator public */; comb_mem #( .DATA_WIDTH(16) @@ -50,7 +54,7 @@ comb_mem #( .X_in(result_int) ); -logic cpu_do_jump_int; +logic cpu_do_jump_int /* verilator public */; instruction_decode CPU ( .instruction_in(PC_content_int), |