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-rw-r--r--Makefile8
-rw-r--r--debounce_tb.v (renamed from debounce.tb.v)2
-rw-r--r--fifo.v1
-rw-r--r--fifo_tb.v (renamed from fifo.tb.v)12
-rw-r--r--fizzbuzz_tb.v (renamed from fizzbuzz.tb.v)2
-rw-r--r--led_toggle_bouncy_tb.v (renamed from led_toggle_bouncy.tb.v)2
-rw-r--r--led_toggle_tb.v (renamed from led_toggle.tb.v)2
-rw-r--r--my_mem_tb.v (renamed from my_mem.tb.v)0
-rw-r--r--par_to_ser_tb.v (renamed from par_to_ser.tb.v)2
-rw-r--r--par_to_ser_to_par_tb.v (renamed from par_to_ser_to_par.tb.v)0
-rw-r--r--ser_to_par_tb.v (renamed from ser_to_par.tb.v)2
-rw-r--r--template_tb.v (renamed from template.tb.v)6
-rw-r--r--tst_delay_tb.v (renamed from tst_delay.tb.v)6
13 files changed, 27 insertions, 18 deletions
diff --git a/Makefile b/Makefile
index 06a693a..94c301c 100644
--- a/Makefile
+++ b/Makefile
@@ -96,14 +96,14 @@ lint: $(PROGRAM).v
%.lxt2: %.vvp
./$< -lxt2
-%.vvp: %.v %.tb.v
- iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*.tb.v
+%.vvp: %.v %_tb.v
+ iverilog -DDUMP_FILE_NAME='"$*.lxt2"' -g2012 -o $*.vvp $*.v $*_tb.v
# verilog unfortunately exits on any warning
# also on warnings "boohoo, you specified timings in some modules and not in others"
# since this is fucking annoying, I choose to ignore the exit code.
-verilator.%: %.v %.tb.v
- verilator --quiet -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(PROGRAM) $(PROGRAM).tb.v || true
+verilator.%: %.v %_tb.v
+ verilator --quiet -DDUMP_FILE_NAME='"dump.vvp"' --trace --timing --main --exe --Mdir verilator.$(*) $(*)_tb.v || true
# need to specify RM for some reason
# verilators makefiles doesn't specify the variable
diff --git a/debounce.tb.v b/debounce_tb.v
index 3376434..a7017c7 100644
--- a/debounce.tb.v
+++ b/debounce_tb.v
@@ -10,7 +10,7 @@ logic signal_o;
integer i = 0;
-debounce #(.STABLE_PERIOD(5)) uut(
+debounce #(.STABLE_PERIOD(5)) uut (
.rst_i(rst_i),
.clk_i(clk_i),
.signal_i(signal_i),
diff --git a/fifo.v b/fifo.v
index 30b963e..bcc2d3f 100644
--- a/fifo.v
+++ b/fifo.v
@@ -27,6 +27,7 @@ localparam DATA_DEPTH_BITS = $clog2(DATA_DEPTH);
// the -1 will make sure it fits
/* verilator lint_off WIDTHTRUNC */
localparam [DATA_DEPTH_BITS-1:0] MAX_ADDRESS = (DATA_DEPTH - 1);
+/* verilator lint_on WIDTHTRUNC */
// need to "count" to number *including* depth
reg [$clog2(DATA_DEPTH + 1)-1:0] r_count;
diff --git a/fifo.tb.v b/fifo_tb.v
index 3238eba..4b1423c 100644
--- a/fifo.tb.v
+++ b/fifo_tb.v
@@ -12,12 +12,16 @@ reg [7:0] data_i;
fifo #(
.DATA_WIDTH(8),
.DATA_DEPTH(8)
-) uut(
+) uut (
.clk_i(clk_i),
.rst_i(rst_i),
.write_i(write_i),
.read_i(read_i),
- .data_i
+ .data_i(data_i),
+
+ .empty_o(),
+ .full_o(),
+ .data_o()
);
string filename;
@@ -28,8 +32,8 @@ initial begin
filename="fifo.lxt2";
`endif
$dumpfile(filename); $dumpvars();
- clk_i <= 0;
- rst_i <= 1'b1;
+ clk_i = 0;
+ rst_i = 1'b1;
read_i = 0;
write_i = 0;
data_i = 0;
diff --git a/fizzbuzz.tb.v b/fizzbuzz_tb.v
index 7855a9b..2a8cdff 100644
--- a/fizzbuzz.tb.v
+++ b/fizzbuzz_tb.v
@@ -9,7 +9,7 @@ logic clk_i;
logic [7:0] num_out;
-fizzbuzz uut(
+fizzbuzz uut (
.num_i(number),
.num_o(num_out),
.fizz_o(),
diff --git a/led_toggle_bouncy.tb.v b/led_toggle_bouncy_tb.v
index 7999454..f300071 100644
--- a/led_toggle_bouncy.tb.v
+++ b/led_toggle_bouncy_tb.v
@@ -7,7 +7,7 @@ logic clk_i;
logic key_i;
logic [5:0] led;
-led_toggle_bouncy uut(
+led_toggle_bouncy uut (
.clk_i(clk_i),
.key_i(key_i),
.led(led)
diff --git a/led_toggle.tb.v b/led_toggle_tb.v
index a883af4..f5f4fd5 100644
--- a/led_toggle.tb.v
+++ b/led_toggle_tb.v
@@ -9,7 +9,7 @@ logic key_i;
logic [5:0] led;
-led_toggle #(.STABLE_PERIOD(2)) uut(
+led_toggle #(.STABLE_PERIOD(2)) uut (
.rst_i(rst_i),
.clk_i(clk_i),
.key_i(key_i),
diff --git a/my_mem.tb.v b/my_mem_tb.v
index c8c2e12..c8c2e12 100644
--- a/my_mem.tb.v
+++ b/my_mem_tb.v
diff --git a/par_to_ser.tb.v b/par_to_ser_tb.v
index b610884..edb1f9b 100644
--- a/par_to_ser.tb.v
+++ b/par_to_ser_tb.v
@@ -9,7 +9,7 @@ logic data_valid_i;
logic [7:0] dat_i;
logic dat_o;
-par_to_ser uut(
+par_to_ser uut (
.clk_i(clk_i),
.rst_i(rst_i),
.data_valid_i(data_valid_i),
diff --git a/par_to_ser_to_par.tb.v b/par_to_ser_to_par_tb.v
index c422d86..c422d86 100644
--- a/par_to_ser_to_par.tb.v
+++ b/par_to_ser_to_par_tb.v
diff --git a/ser_to_par.tb.v b/ser_to_par_tb.v
index de730c6..e82b56e 100644
--- a/ser_to_par.tb.v
+++ b/ser_to_par_tb.v
@@ -9,7 +9,7 @@ logic dat_i;
logic dat_valid;
logic [7:0] dat_o;
-ser_to_par uut(
+ser_to_par uut (
.clk_i(clk_i),
.rst_i(rst_i),
.dat_i(dat_i),
diff --git a/template.tb.v b/template_tb.v
index fb37668..3526168 100644
--- a/template.tb.v
+++ b/template_tb.v
@@ -6,7 +6,7 @@ module template_tb (
reg clk_i;
reg rst_i;
-template uut(
+template uut (
.clk_i(clk_i),
.rst_i(rst_i)
);
@@ -19,8 +19,8 @@ initial begin
filename="template.lxt2";
`endif
$dumpfile(filename); $dumpvars();
- clk_i <= 0;
- rst_i <= 1'b1;
+ clk_i = 0;
+ rst_i = 1'b1;
end
diff --git a/tst_delay.tb.v b/tst_delay_tb.v
index 41a133a..03ef185 100644
--- a/tst_delay.tb.v
+++ b/tst_delay_tb.v
@@ -8,7 +8,7 @@ reg clk_i;
reg data_i;
wire data_o;
-tst_delay uut(
+tst_delay uut (
.clk_i(clk_i),
.data_i(data_i),
.data_o(data_o)
@@ -33,9 +33,13 @@ initial begin
data_i = 1;
#2
data_i = 0;
+
+ /* verilator lint_off INITIALDLY */
// note the <= assignment
#19
data_i <= 1;
+ /* verilator lint_on INITIALDLY */
+
#1
data_i = 0;
// note the = assignment