1 files changed, 5 insertions, 1 deletions
diff --git a/README.txt b/README.txt
index fd579e2..1445c46 100644
--- a/README.txt
+++ b/README.txt
@@ -14,4 +14,8 @@ Questions:
 - Why do so many examples use always @(posedge clk or nededge rst).
   i.e., why is the clk always included?
   - "async reset" - asynchronous events might be missed, and they
-    don't work well with clocked registers.
-\ No newline at end of file
+    don't work well with clocked registers.
+- Does yosys and other tools "automatically" determine the
+  "perfect" wire/register (bus) width if I just specify e.g.
+  wire BLA = 1374;
+  ?
+\ No newline at end of file