diff options
| -rw-r--r-- | .gitignore | 4 | ||||
| -rw-r--r-- | Makefile | 19 | ||||
| -rw-r--r-- | led.v | 28 |
3 files changed, 51 insertions, 0 deletions
diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..15fc2c5 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ +*.json +*.cst* +*.fs + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..949996d --- /dev/null +++ b/Makefile @@ -0,0 +1,19 @@ +all: led.fs + +tangnano9k.cst: + wget https://github.com/YosysHQ/apicula/raw/refs/heads/master/examples/tangnano9k.cst || \ + curl -LO https://github.com/YosysHQ/apicula/raw/refs/heads/master/examples/tangnano9k.cst + +led.json: led.v + yosys -p "read_verilog led.v; synth_gowin -top led -json led.json" + +pnrled.json: tangnano9k.cst led.json + nextpnr-himbaechel --json led.json --write pnrled.json \ + --device GW1NR-LV9QN88PC6/I5 --vopt family=GW1N-9C \ + --vopt cst=tangnano9k.cst + +led.fs: pnrled.json + gowin_pack -d GW1N-9C -o led.fs pnrled.json + +flash: led.fs + openFPGALoader -b tangnano9k -f led.fs @@ -0,0 +1,28 @@ +module led ( + input clk, // clk input + input rst_i, // reset input + output reg [5:0] led // 6 LEDS pin +); + +reg [23:0] counter; + +always @(posedge clk or negedge rst_i) begin + if (!rst_i) + counter <= 24'd0; + else if (counter < 24'd1349_9999) // 0.5s delay + counter <= counter + 1'b1; + else + counter <= 24'd0; +end + +always @(posedge clk or negedge rst_i) begin + if (!rst_i) + led <= 6'b111110; + else if (counter == 24'd1349_9999) // 0.5s delay + led[5:0] <= led[5:0] - 1; + else + led <= led; +end + +endmodule + |