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@@ -3,9 +3,15 @@ Learnings: - Anything that needs to "store" a state must be a reg? => wire's can't be assigned in always blocks, yosys complains - regs must not lead to wires? (unsure where I read that) + - https://blog.waynejohnson.net/doku.php/verilog_wire_and_reg + -> wires of an outer module can be connecting to an inner module. + -> reg can be input to an inner module + -> regs can't be outputs - Clock on the tang9k is 27 MHz Questions: - Why do so many examples use always @(posedge clk or nededge rst). i.e., why is the clk always included? + - "async reset" - asynchronous events might be missed, and they + don't work well with clocked registers.
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