summaryrefslogtreecommitdiff
path: root/eater_cpu
diff options
context:
space:
mode:
Diffstat (limited to 'eater_cpu')
-rw-r--r--eater_cpu/Makefile2
-rw-r--r--eater_cpu/bus_writer.sv13
-rw-r--r--eater_cpu/eater_computer_tb.sv8
-rw-r--r--eater_cpu/zbuffer.sv21
4 files changed, 26 insertions, 18 deletions
diff --git a/eater_cpu/Makefile b/eater_cpu/Makefile
index c39f541..2a958de 100644
--- a/eater_cpu/Makefile
+++ b/eater_cpu/Makefile
@@ -1,2 +1,2 @@
-cpu: eater_computer_tb.sv eater_computer.sv bus_writer.sv eater_register.v eater_alu.sv ../playground/my_mem.v ../nandgame/counter.sv
+cpu: eater_computer_tb.sv eater_computer.sv zbuffer.sv eater_register.v eater_alu.sv ../playground/my_mem.v ../nandgame/counter.sv
iverilog -o $@ -g2012 $^
diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
deleted file mode 100644
index fe34202..0000000
--- a/eater_cpu/bus_writer.sv
+++ /dev/null
@@ -1,13 +0,0 @@
-// Debugging the Ben Eater bus, by manually writing data to it.
-
-`timescale 1us/1us
-
-module bus_writer (
- input wire [7:0] in_value,
- input wire in_write_to_output,
- output wire [7:0] out_value
-);
-
-assign out_value = in_write_to_output ? in_value : 8'bZ;
-
-endmodule
diff --git a/eater_cpu/eater_computer_tb.sv b/eater_cpu/eater_computer_tb.sv
index d05dc52..74ffb8a 100644
--- a/eater_cpu/eater_computer_tb.sv
+++ b/eater_cpu/eater_computer_tb.sv
@@ -14,10 +14,10 @@ eater_computer uut (
logic [7:0] debug_value;
logic debug_enable;
-bus_writer debugger (
- .in_value(debug_value),
- .in_write_to_output(debug_enable),
- .out_value(uut.bus)
+zbuffer debugger (
+ .data_in(debug_value),
+ .en_output_in(debug_enable),
+ .data_out(uut.bus)
);
initial begin
diff --git a/eater_cpu/zbuffer.sv b/eater_cpu/zbuffer.sv
new file mode 100644
index 0000000..fd7e0f6
--- /dev/null
+++ b/eater_cpu/zbuffer.sv
@@ -0,0 +1,21 @@
+`timescale 1us/1us
+
+`ifndef ZBUFFER
+`define ZBUFFER
+
+module zbuffer #(
+ parameter BUFFER_WIDTH = 8
+) (
+ // async - output data
+ input wire en_output_in,
+
+ input wire [(BUFFER_WIDTH-1) : 0] data_in,
+ // output (to bus) if output enabled.
+ output wire [(BUFFER_WIDTH-1) : 0] data_out
+);
+
+assign data_out = en_output_in ? data_in : {BUFFER_WIDTH{1'bz}};
+
+endmodule
+
+`endif