diff options
Diffstat (limited to 'eater_cpu')
| -rw-r--r-- | eater_cpu/eater_computer.sv | 15 | ||||
| -rw-r--r-- | eater_cpu/eater_computer_tb.sv | 66 |
2 files changed, 72 insertions, 9 deletions
diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv index 7e49f2b..4985306 100644 --- a/eater_cpu/eater_computer.sv +++ b/eater_cpu/eater_computer.sv @@ -48,18 +48,27 @@ eater_register B ( // .data(bus) ); -assign bus[3:0] = INS_out[3:0]; +wire [7:0] INS_out_full; eater_register INS ( .clk_in(clk_in), .en_store_in(bus_to_INS), .en_output_in(INS_to_bus), .data_in(bus), - .bus_out(INS_out), - .always_out() + .bus_out(), + .always_out(INS_out_full) // .data(INS_out) ); +// 4 LSB go from INS to BUS +wire [7:0] INS_to_bus_interm = {4'b0, INS_out_full[3:0]}; + +zbuffer INS_to_bus_buffer ( + .data_in(INS_to_bus_interm), + .en_output_in(INS_to_bus), + .data_out(bus) +); + tri [7:0] MEM_ADR_out; tri [3:0] RAM_adr_in = MEM_ADR_out[3:0]; diff --git a/eater_cpu/eater_computer_tb.sv b/eater_cpu/eater_computer_tb.sv index 5b14620..47ef16f 100644 --- a/eater_cpu/eater_computer_tb.sv +++ b/eater_cpu/eater_computer_tb.sv @@ -48,8 +48,20 @@ always #2 clk_in = ~clk_in; initial begin @(negedge clk_in); - debug_value = 'haa; debug_enable = 1; + + @(negedge clk_in); + debug_value = 'h00; + uut.bus_to_MAR = 1; + + @(negedge clk_in); + uut.bus_to_MAR = 0; + debug_value = 'h04; + uut.bus_to_PC = 1; + + @(negedge clk_in); + uut.bus_to_PC = 0; + debug_value = 'haa; uut.bus_to_A = 1; @(negedge clk_in); @@ -63,31 +75,73 @@ initial begin uut.bus_to_INS = 1; @(negedge clk_in); + uut.bus_to_INS = 0; + debug_value = 'hdd; + uut.bus_to_RAM = 1; + + @(negedge clk_in); + uut.bus_to_RAM = 0; + + @(negedge clk_in); debug_enable = 0; debug_value = 'z; - uut.bus_to_INS = 0; @(negedge clk_in); uut.A_to_bus = 1; @(negedge clk_in); assert (uut.bus == 'haa) - else $error("Expected 0xaa, got 0x%02x on bus", uut.bus); + else $error("Expected 0xaa (from REG A), got 0x%02x on bus", uut.bus); uut.A_to_bus = 0; + uut.B_to_bus = 1; + + @(negedge clk_in); + assert (uut.bus == 'hbb) + else $error("Expected 0xbb (from REG B), got 0x%02x on bus", uut.bus); + uut.B_to_bus = 0; + uut.INS_to_bus = 1; + + @(negedge clk_in); + assert (uut.bus == 'h0c) + else $error("Expected 0x0c (from INS), got 0x%02x on bus", uut.bus); + // ERROR: TODO: should I expect 'zc or '0c ? + uut.INS_to_bus = 0; @(negedge clk_in); uut.ALU_to_bus = 1; @(negedge clk_in); assert (uut.bus == 8'('haa + 'hbb)) - else $error("Expected 0x%02x, got 0x%02x on bus", 8'('haa + 'hbb), uut.bus); + else $error("Expected 0x%02x (from ALU), got 0x%02x on bus", 8'('haa + 'hbb), uut.bus); uut.ALU_to_bus = 0; uut.PC_to_bus = 1; @(negedge clk_in); - assert (uut.bus == 'h00) - else $error("Expected 0x00, got 0x%02x on bus", uut.bus); + assert (uut.bus == 'h04) + else $error("Expected 0x04 (from PC), got 0x%02x on bus", uut.bus); uut.PC_to_bus = 0; + uut.RAM_to_bus = 1; + + @(negedge clk_in); + assert (uut.bus == 'hdd) + else $error("Expected 0xdd (from RAM), got 0x%02x on bus", uut.bus); + uut.RAM_to_bus = 0; + + @(negedge clk_in); + debug_enable = 1; + debug_value = 'h01; + uut.bus_to_MAR = 1; + + @(negedge clk_in); + debug_enable = 0; + debug_value = 'bz; + uut.bus_to_MAR = 0; + uut.RAM_to_bus = 1; + + @(negedge clk_in); + $info("Got 0x%02x from RAM", uut.bus); + assert (uut.bus !== 'hdd) + else $error("Did NOT expectd 0xdd (from RAM)"); #10 $finish(); |