3 files changed, 51 insertions, 1 deletions
diff --git a/eater_cpu/bus_writer.sv b/eater_cpu/bus_writer.sv
new file mode 100644
index 0000000..6104301
--- /dev/null
+++ b/eater_cpu/bus_writer.sv
@@ -0,0 +1,9 @@
+module bus_writer (
+    input [7:0] in_value,
+    input in_write_to_output,
+    output [7:0] out_value
+);
+
+assign out_value = in_write_to_output ? in_value : 8'bZ;
+
+endmodule
+\ No newline at end of file
diff --git a/eater_cpu/eater_computer.sv b/eater_cpu/eater_computer.sv
index b2f9a5a..cace515 100644
--- a/eater_cpu/eater_computer.sv
+++ b/eater_cpu/eater_computer.sv
@@ -23,6 +23,7 @@ eater_register A (
   .en_output_i(A_to_bus),
   .data_i(bus),
   .data_o(bus)
+  // .data(bus)
 );
 
 eater_register B (
@@ -31,6 +32,7 @@ eater_register B (
   .en_output_i(B_to_bus),
   .data_i(bus),
   .data_o(bus)
+  // .data(bus)
 );
 
 tri [7:0] ins_bus_out;
@@ -42,24 +44,59 @@ eater_register INS (
   .en_output_i(INS_to_bus),
   .data_i(bus),
   .data_o(ins_bus_out)
+  // .data(ins_bus_out)
 );
 
 `ifdef VERILATOR
+
+logic [7:0] debug_value;
+logic debug_enable;
+
+bus_writer debugger (
+  .in_value(debug_value),
+  .in_write_to_output(debug_enable),
+  .out_value(bus)
+);
+
 initial begin
   $dumpfile("simpc.vvp");
   $dumpvars();
 
   A_to_bus = 0;
   B_to_bus = 0;
+  INS_to_bus = 0;
   bus_to_A = 0;
   bus_to_B = 0;
+  bus_to_INS = 0;
   clk_in = 0;
+  debug_enable = 0;
+  debug_value = 'z;
 end
 
 always #2 clk_in = ~clk_in;
 
 initial begin
 
+  @(negedge clk_in);
+  debug_value = 'haa;
+  debug_enable = 1;
+
+  bus_to_A = 1;
+  @(negedge clk_in);
+  bus_to_A = 0;
+  debug_value = 'hbb;
+  bus_to_B = 1;
+  @(negedge clk_in);
+  bus_to_B = 0;
+  debug_value = 'hcc;
+  bus_to_INS = 1;
+  @(negedge clk_in);
+  debug_enable = 0;
+  debug_value = 'z;
+  bus_to_INS = 0;
+  @(negedge clk_in);
+  A_to_bus = 1;
+  @(negedge clk_in);
   #10
   $finish();
 end
diff --git a/eater_cpu/eater_register.v b/eater_cpu/eater_register.v
index 6025ed1..17da7bd 100644
--- a/eater_cpu/eater_register.v
+++ b/eater_cpu/eater_register.v
@@ -15,6 +15,8 @@ module eater_register #(
 
   input [(DATA_WIDTH-1) : 0] data_i,
   output [(DATA_WIDTH-1) : 0] data_o
+  // inout [(DATA_WIDTH-1) : 0] data
+  
 );
 
 reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
@@ -22,10 +24,12 @@ reg [(DATA_WIDTH-1) : 0] r_datastore /* verilator public */;
 always @(posedge clk_i) begin
   if (en_store_i) begin
     r_datastore <= data_i;
+    // r_datastore <= data;
   end
 end
 
-assign data_o = en_output_i ? r_datastore : 'z;
+assign data_o = en_output_i ? r_datastore : 8'bz;
+// assign data = en_output_i ? r_datastore : 8'bz;
 
 endmodule