1 files changed, 16 insertions, 1 deletions
diff --git a/nandgame/counter.sv b/nandgame/counter.sv
index 8fa1d2b..78f054e 100644
--- a/nandgame/counter.sv
+++ b/nandgame/counter.sv
@@ -12,7 +12,7 @@ module  counter #(
   // and "outputs" on falling clock,
   // use "regular" stuff??? 
   input wire cl,
-  output reg [(DATA_WIDTH-1):0] RES
+  output wire [(DATA_WIDTH-1):0] count
 );
 
 
@@ -32,4 +32,19 @@ st	cl
 output is the current output of the component. next becomes the current output when cl changes to 0.
 */
 
+reg [(DATA_WIDTH-1):0] r_ctr;
+
+initial begin
+  r_ctr = 0;
+end
+
+always @(negedge cl) begin
+  if (st)
+    r_ctr <= X;
+  else
+    r_ctr <= r_ctr + 1;
+end
+
+assign count = r_ctr;
+
 endmodule