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diff --git a/par_to_ser.v b/par_to_ser.v
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+// parallel to serial converter
+// Learning:
+// I think I need a "start" signal (do_send_i),
+// otherwise I'll never know when to copy the input data
+// to out internal register
+
+module par_to_ser (
+  input rst_i,
+  input clk_i,
+  input do_send_i,
+  input [7:0] dat_i,
+  output reg dat_o
+);
+
+reg sending = 1'b0;
+reg [7:0] send_data = 8'hff;
+
+always @(posedge clk_i or negedge rst_i) begin
+  if (!rst_i) begin
+    dat_o <= 1'b1;
+  end else if (do_send_i && !sending) begin
+    sending <= 1;
+    send_data <= dat_i;
+  end else if (sending) begin
+    dat_o = send_data[0];
+    send_data[6:0] <= send_data[7:1];
+    // arbitrary decision: register is filled with a 1
+    send_data[7] = 1'b1;
+  end
+end
+
+endmodule