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+// serial to parallel converter
+// Learning:
+// I don't like this.
+// I think I need a signal / way to say "I'm finished"?
+//
+
+module ser_to_par (
+  input rst_i,
+  input clk_i,
+  input dat_i,
+  output reg[7:0] dat_o
+);
+
+always @(posedge clk_i or negedge rst_i) begin
+  if (!rst_i) begin
+    dat_o <= 8'b0;
+  end else begin
+    dat_o[0] <= dat_i;
+    dat_o[7:1] <= dat_o[6:0];
+  end
+end
+
+endmodule