| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 25 hours | Ignore build dir | uvok | |
| 25 hours | Ignore compiled python stuff | uvok | |
| 2 days | ignore clangd cache file | uvok | |
| 4 days | Update gitignore | uvok | |
| 5 days | Update gitingore | uvok | |
| 8 days | Start by bin creator and disassembler | uvok | |
| 2025-12-28 | make: Add rules for verilator simulation | uvok | |
| 2025-12-26 | Add simulation targets | uvok | |
| 2025-12-25 | makefile: Finally fix makefiles? | uvok | |
| 2025-12-24 | Write placed and routed SVGs | uvok | |
| 2025-12-23 | Add FPGA basics | uvok | |
 |
index : fpga-exper | |
| FPGA experiments |
| summaryrefslogtreecommitdiff |
path: root/.gitignore