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4 daysUpdate gitingoreuvok
8 daysStart by bin creator and disassembleruvok
2025-12-28make: Add rules for verilator simulationuvok
2025-12-26Add simulation targetsuvok
2025-12-25makefile: Finally fix makefiles?uvok
2025-12-24Write placed and routed SVGsuvok
2025-12-23Add FPGA basicsuvok