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AgeCommit message (Collapse)Author
13 daysIgnore build diruvok
13 daysIgnore compiled python stuffuvok
14 daysignore clangd cache fileuvok
2026-01-08Update gitignoreuvok
2026-01-07Update gitingoreuvok
2026-01-04Start by bin creator and disassembleruvok
2025-12-28make: Add rules for verilator simulationuvok
2025-12-26Add simulation targetsuvok
2025-12-25makefile: Finally fix makefiles?uvok
2025-12-24Write placed and routed SVGsuvok
2025-12-23Add FPGA basicsuvok