fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
38 hours	Show ROM/RAM	uvok
38 hours	Redesign UI, add program content	uvok
38 hours	Add third assembler example	uvok
38 hours	Use sync output for ROM	uvok
38 hours	CPU: Annotate unconnected pin	uvok
38 hours	Remove rando int	uvok
38 hours	computer: Fix x/y	uvok
38 hours	comb_mem: Use async data o	uvok
38 hours	Add second example	uvok
38 hours	mem: Add async data output	uvok
38 hours	comb_mem: Test when output occurs	uvok
38 hours	reformatcomputer, get rid of i	uvok
39 hours	dias: Only return halt for simplified	uvok
47 hours	Fixup order/break point	uvok
47 hours	don't draw / refresh UI after a halt	uvok
47 hours	sim: Properly display results	uvok
2 days	example: Make sure state is shown	uvok
2 days	ignore clangd cache file	uvok
2 days	main: Write tracefile	uvok
2 days	verilator: Enable tracing	uvok
2 days	Implement halting	uvok
2 days	Docu	uvok
2 days	Add WIP hack ALU	uvok
3 days	Add assembler exampel	uvok
3 days	bit 14 unset (w/ 15 set) = illegal ins	uvok
3 days	simu: longer simu, stop condition	uvok
3 days	ncur: print instruction across whole line	uvok
3 days	Add LLM assembler	uvok
3 days	make: Unified makefile	uvok
3 days	move stuff around	uvok
3 days	Extract UI drawing	uvok
4 days	include ALU in output	uvok
4 days	Add really nice ncurses UI	uvok
4 days	Update gitignore	uvok
4 days	nandgame: ncurses interface	uvok
4 days	disas, c: Fix compilation, missing header	uvok
4 days	makefile: Add instruction for simulated PC	uvok
5 days	Add cmp instruction	uvok
5 days	disas: endianness	uvok
5 days	cb: specify endianness via arg	uvok
5 days	fix endianness of binary creator	uvok
5 days	Use gen'ed disaas	uvok
5 days	add LLM-gened disas	uvok
5 days	view result register	uvok
5 days	add computer launcher	uvok
5 days	py: Add single-instruction disas	uvok
5 days	disas: Fix for ye olde pyhton	uvok
5 days	Annozate stuff for verilator	uvok
5 days	Update gitingore	uvok
6 days	Documentation	uvok