| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 11 days | Invert u | uvok | |
| 11 days | add ALU | uvok | |
| 11 days | fix comment | uvok | |
| 11 days | guard types | uvok | |
| 11 days | Add arithmetic unit, disable gtkwave | uvok | |
| 11 days | Add nandgame files | uvok | |
| need/want systemverilog | |||
| 11 days | remove superfluous ws | uvok | |
| 11 days | Add nandgame save | uvok | |
| 13 days | linting, use different naming | uvok | |
| use _tb.v instead of .tb.v, to stop verilator from shouting the module name doesn't match | |||
| 13 days | template: Introduce nedge | uvok | |
| 13 days | tst_delay: Fix testbench name | uvok | |
| 13 days | Fix testbench | uvok | |
| 13 days | fizzbuzz: Fix testbench | uvok | |
| also, remove testing output | |||
| 13 days | led_tgl_bounce:Fix testbench | uvok | |
| same aswith the others | |||
| 13 days | led_toggle: Use edge timing, logic | uvok | |
| 13 days | p2s2p: Fix testbench | uvok | |
| iverilog syntax error (needs space) timing use logic, | |||
| 13 days | my_mem: Use nededge for timing | uvok | |
| 13 days | p2s: Fix test bench | uvok | |
| use negedge timing | |||
| 13 days | s2p: Fix testbench | uvok | |
| needed data valid signal | |||
| 13 days | make: shut up gtkwave | uvok | |
| 14 days | Add fucked test bench | uvok | |
| 14 days | mem: Add debug for iverilog | uvok | |
| 14 days | Fix fifo using memory, fix test bench | uvok | |
| 2025-12-29 | make,verilator: Use 4 make jobs | uvok | |
| 2025-12-29 | Add memory | uvok | |
| 2025-12-29 | make: make verilator quiet | uvok | |
| 2025-12-29 | Shut up verilators timescale warnings | uvok | |
| 2025-12-29 | fifo :Split in blocks | uvok | |
| 2025-12-29 | fifo: r/w/address logic | uvok | |
| 2025-12-29 | fifo: try implement r/w logic | uvok | |
| 2025-12-29 | fifo: Count bytes | uvok | |
| 2025-12-28 | Add a p2s2p test ench | uvok | |
| 2025-12-28 | p2s: Check if bits are correct | uvok | |
| 2025-12-28 | s2p: count read bytes | uvok | |
| no idea for what purpose. | |||
| 2025-12-28 | p2s: Add valid output signal | uvok | |
| 2025-12-28 | Add parameter to s2p | uvok | |
| 2025-12-28 | add fifo | uvok | |
| 2025-12-28 | make: Add rules for verilator simulation | uvok | |
| 2025-12-28 | makefile: specify dumpfile on cmdline | uvok | |
| 2025-12-28 | tb: Add dumpfilename macro | uvok | |
| 2025-12-28 | Add edge test | uvok | |
| 2025-12-27 | lint testbenches | uvok | |
| param instantiation | |||
| 2025-12-27 | veri: Fix linting errors | uvok | |
| - use instantiation parameter instead of defparam - avoid duplicate name (module/output) | |||
| 2025-12-27 | Add verilator linting | uvok | |
| 2025-12-27 | p2s: Always use correct shift width | uvok | |
| 2025-12-27 | p2s: rewrite logic | uvok | |
| split blocks. Better separate counting/sending logic. | |||
| 2025-12-27 | p2s: Testbench all nums | uvok | |
| 2025-12-27 | Re-iterate par2ser | uvok | |
| 2025-12-27 | fizzbuzz: Add another test output | uvok | |
| 2025-12-27 | Implement fizzbuzz | uvok | |
