fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
11 days	alu: Fix assignment error	uvok
11 days	include types in tbs again	uvok
11 days	tbs: remove e empty parens	uvok
11 days	Invert u	uvok
11 days	add ALU	uvok
11 days	fix comment	uvok
11 days	guard types	uvok
11 days	Add arithmetic unit, disable gtkwave	uvok
11 days	Add nandgame files	uvok
11 days	remove superfluous ws	uvok
11 days	Add nandgame save	uvok
13 days	linting, use different naming	uvok
13 days	template: Introduce nedge	uvok
13 days	tst_delay: Fix testbench name	uvok
13 days	Fix testbench	uvok
13 days	fizzbuzz: Fix testbench	uvok
13 days	led_tgl_bounce:Fix testbench	uvok
13 days	led_toggle: Use edge timing, logic	uvok
13 days	p2s2p: Fix testbench	uvok
13 days	my_mem: Use nededge for timing	uvok
13 days	p2s: Fix test bench	uvok
13 days	s2p: Fix testbench	uvok
13 days	make: shut up gtkwave	uvok
14 days	Add fucked test bench	uvok
14 days	mem: Add debug for iverilog	uvok
14 days	Fix fifo using memory, fix test bench	uvok
14 days	make,verilator: Use 4 make jobs	uvok
14 days	Add memory	uvok
14 days	make: make verilator quiet	uvok
14 days	Shut up verilators timescale warnings	uvok
14 days	fifo :Split in blocks	uvok
14 days	fifo: r/w/address logic	uvok
14 days	fifo: try implement r/w logic	uvok
14 days	fifo: Count bytes	uvok
2025-12-28	Add a p2s2p test ench	uvok
2025-12-28	p2s: Check if bits are correct	uvok
2025-12-28	s2p: count read bytes	uvok
2025-12-28	p2s: Add valid output signal	uvok
2025-12-28	Add parameter to s2p	uvok
2025-12-28	add fifo	uvok
2025-12-28	make: Add rules for verilator simulation	uvok
2025-12-28	makefile: specify dumpfile on cmdline	uvok
2025-12-28	tb: Add dumpfilename macro	uvok
2025-12-28	Add edge test	uvok
2025-12-27	lint testbenches	uvok
2025-12-27	veri: Fix linting errors	uvok
2025-12-27	Add verilator linting	uvok
2025-12-27	p2s: Always use correct shift width	uvok
2025-12-27	p2s: rewrite logic	uvok
2025-12-27	p2s: Testbench all nums	uvok