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AgeCommit message (Expand)Author
2025-12-26Improve testbenchuvok
2025-12-26dd first version of testbenchuvok
2025-12-26Add simulation targetsuvok
2025-12-26makefile: centralize nextpnr argsuvok
2025-12-25Note that led_toggle is a bouncy variantuvok
2025-12-25Use variables for device and familyuvok
2025-12-25Add clock constraints fileuvok
2025-12-25led: rename vars to make more senseuvok
2025-12-25toggl: Fix state of 5fth LEDuvok
2025-12-25Add error for "used but no driver"uvok
2025-12-25Add working LED exampleuvok
2025-12-25yosys: Use less specialized regex for erroruvok
2025-12-25Questionsuvok
2025-12-25Make conflicting drivers an erroruvok
2025-12-25Use yosys for dep generation after alluvok
2025-12-25Write my own dep resolve scriptuvok
2025-12-25Remove explicit synth and deps ruleuvok
2025-12-25makefile: Finally fix makefiles?uvok
2025-12-25makefile: Try fix dep ruleuvok
2025-12-25Massiely reorganize makefileuvok
2025-12-25Fix flash target to use PROGRAM variableuvok
2025-12-25Add non-working LED exampleuvok
2025-12-24Use localparam for divisoruvok
2025-12-24Document clock frequvok
2025-12-24add show commanduvok
2025-12-24add readmeuvok
2025-12-24clkdiv: output must be a registeruvok
2025-12-24Don't write to persistant flashuvok
2025-12-24Adjst Makefileuvok
2025-12-24Make clock divider separate moduleuvok
2025-12-24Write placed and routed SVGsuvok
2025-12-23Use patternuvok
2025-12-23Add FPGA basicsuvok
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