fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
19 hours	Add second example	uvok
19 hours	mem: Add async data output	uvok
19 hours	comb_mem: Test when output occurs	uvok
19 hours	cmake: Gen compile commands	uvok
19 hours	computer: get rid of i	uvok
19 hours	properly use cmake as mentioned in the docs	uvok
19 hours	Utilize cbreak mode	uvok
20 hours	fix olde makefile	uvok
20 hours	Add paused state, print help	uvok
20 hours	Rename functions	uvok
20 hours	Improve Cmake file	uvok
20 hours	Move finish into UI	uvok
20 hours	Move around stuff, split UI	uvok
20 hours	Add cmake build for verilator	uvok
20 hours	Dumpfile on VERILATOR	uvok
21 hours	Ignore build dir	uvok
21 hours	Ignore compiled python stuff	uvok
21 hours	Reorganize cpp files	uvok
35 hours	dias: Only return halt for simplified	uvok
43 hours	Fixup order/break point	uvok
43 hours	don't draw / refresh UI after a halt	uvok
43 hours	sim: Properly display results	uvok
45 hours	example: Make sure state is shown	uvok
45 hours	ignore clangd cache file	uvok
45 hours	main: Write tracefile	uvok
45 hours	verilator: Enable tracing	uvok
45 hours	Implement halting	uvok
45 hours	Docu	uvok
45 hours	Add WIP hack ALU	uvok
3 days	Add assembler exampel	uvok
3 days	bit 14 unset (w/ 15 set) = illegal ins	uvok
3 days	simu: longer simu, stop condition	uvok
3 days	ncur: print instruction across whole line	uvok
3 days	Add LLM assembler	uvok
3 days	make: Unified makefile	uvok
3 days	move stuff around	uvok
3 days	Extract UI drawing	uvok
3 days	include ALU in output	uvok
3 days	Add really nice ncurses UI	uvok
3 days	Update gitignore	uvok
3 days	nandgame: ncurses interface	uvok
3 days	disas, c: Fix compilation, missing header	uvok
3 days	makefile: Add instruction for simulated PC	uvok
4 days	Add cmp instruction	uvok
4 days	disas: endianness	uvok
4 days	cb: specify endianness via arg	uvok
5 days	fix endianness of binary creator	uvok
5 days	Use gen'ed disaas	uvok
5 days	add LLM-gened disas	uvok
5 days	view result register	uvok