fpga-exper - FPGA experiments

Age	Commit message (Expand)	Author
22 hours	Add cmake build for verilator	uvok
22 hours	Dumpfile on VERILATOR	uvok
22 hours	Ignore build dir	uvok
23 hours	Ignore compiled python stuff	uvok
23 hours	Reorganize cpp files	uvok
36 hours	Show ROM/RAM	uvok
36 hours	Redesign UI, add program content	uvok
36 hours	Add third assembler example	uvok
36 hours	Use sync output for ROM	uvok
36 hours	CPU: Annotate unconnected pin	uvok
36 hours	Remove rando int	uvok
36 hours	computer: Fix x/y	uvok
36 hours	comb_mem: Use async data o	uvok
36 hours	Add second example	uvok
36 hours	mem: Add async data output	uvok
36 hours	comb_mem: Test when output occurs	uvok
36 hours	reformatcomputer, get rid of i	uvok
37 hours	dias: Only return halt for simplified	uvok
45 hours	Fixup order/break point	uvok
45 hours	don't draw / refresh UI after a halt	uvok
45 hours	sim: Properly display results	uvok
47 hours	example: Make sure state is shown	uvok
47 hours	ignore clangd cache file	uvok
47 hours	main: Write tracefile	uvok
47 hours	verilator: Enable tracing	uvok
47 hours	Implement halting	uvok
47 hours	Docu	uvok
47 hours	Add WIP hack ALU	uvok
3 days	Add assembler exampel	uvok
3 days	bit 14 unset (w/ 15 set) = illegal ins	uvok
3 days	simu: longer simu, stop condition	uvok
3 days	ncur: print instruction across whole line	uvok
3 days	Add LLM assembler	uvok
3 days	make: Unified makefile	uvok
3 days	move stuff around	uvok
3 days	Extract UI drawing	uvok
4 days	include ALU in output	uvok
4 days	Add really nice ncurses UI	uvok
4 days	Update gitignore	uvok
4 days	nandgame: ncurses interface	uvok
4 days	disas, c: Fix compilation, missing header	uvok
4 days	makefile: Add instruction for simulated PC	uvok
5 days	Add cmp instruction	uvok
5 days	disas: endianness	uvok
5 days	cb: specify endianness via arg	uvok
5 days	fix endianness of binary creator	uvok
5 days	Use gen'ed disaas	uvok
5 days	add LLM-gened disas	uvok
5 days	view result register	uvok
5 days	add computer launcher	uvok