fpga-exper - FPGA experiments

Age	Commit message (Collapse)	Author
48 hours	Explain separate PC++ state	uvok
	need to get correct next state, once INS is loaded.
48 hours	Revert "eater: Combine counting in prev. state"	uvok
	This reverts commit 1f0fc1edcea04e5c1f04803f0bdda337c2245f09.
4 days	Add halt state and flag	uvok

4 days	eater: Combine counting in prev. state	uvok
	save 1 cycle, as explained in video. also, only print lo->hi clk states to term.
4 days	eater: Add subtract flag	uvok

4 days	eater: Print most control signals	uvok

4 days	eater,sim: Make decoder state actually public-flar	uvok

4 days	eater,sim: Reformat and extract func	uvok

4 days	eater: Add verilator/cmake project	uvok

4 days	eater: Implement leftover states and state transitions	uvok

4 days	eater: Add logic to switch between manual and automatic flags	uvok

4 days	eater: Use control flag struct in computer	uvok

4 days	Add instruction decoder with FSM	uvok

4 days	Fix eater_types for Icarus	uvok

4 days	Add typer, preparation for SM	uvok

5 days	eater: update docs	uvok

5 days	eater: Add simpc makefile snippet	uvok

5 days	eater: Make ALUresult verilator-public	uvok

5 days	eater: Make bs a tri0	uvok
	because eater_computer has pull-downs on bus
5 days	eater: Add OUT reg	uvok

5 days	eater: document	uvok

5 days	eater: Test more signals	uvok

5 days	eater:PC clock runs on neg clock	uvok

5 days	eater: Use separate "zbuffer" module	uvok
	keeps code a bit cleaner
5 days	counter: Add "count_enable" pin	uvok

5 days	Add zbuffer spec	uvok
	remove "debug_bus"
6 days	eater: Add PC, fix signals for MEM/ADR, add readme	uvok

7 days	Add RAM and RAM_ADR register	uvok

7 days	eater: Connect RAM	uvok

7 days	eater: Include RAM	uvok

7 days	(System)Verilog: Be explicit about wire/logic	uvok

7 days	eater: Use "actual -" for alu	uvok
	better synthesis?
7 days	Add link to (S)Verilog datatype	uvok

7 days	eater: Extract computer testbench	uvok

7 days	eater_alu: Use 2complneg instead of subtract	uvok

7 days	eater: Add ALU	uvok
	while doing so, add always_out port for regs
7 days	parser: Add support for bin,oct and fix hex nums	uvok

7 days	parser:restart instead of errok	uvok
	parser needs to be in state 0 again to continue parsing.
7 days	add deliberately broken example	uvok

7 days	parse,lex: Make # separate token	uvok

7 days	Add exmple with equ directive	uvok

7 days	Better tb for eater cpu	uvok

8 days	Add instruction register	uvok

8 days	allow capital letters start in symbol names	uvok

8 days	assembler: Avoid NoneError	uvok
	check result
8 days	eater: reg data out en is async	uvok

8 days	Add 1st sketch of eater cpu	uvok

8 days	hack: Fix verilator annotation	uvok

8 days	Fix issues, linting, use argparse, with other py exes	uvok

8 days	Fix name of assembler. usage	uvok